Method for chip singulation

1. A method of singulating at least one chip from a stack of layers, the stack comprising a front end of line upon a substrate layer, the substrate layer having a first surface and a second surface, the front end of line being positioned on top of the first surface, and a back end of line on top of the front end of line, the method comprising:

etching singulating trenches through the back end of line, through the front end of line and at least partially through the substrate layer of the stack;

depositing a passivation layer on the stack provided with the etched singulating trenches, such that sidewalls of the trenches are at least partially passivated; and

releasing the at least one chip from the stack of layers by reducing the thickness of the substrate layer from the second surface onwards to the bottom of the etched singulating trenches until the at least one chip is released from the stack.

2. The method as in claim 1 , wherein etching the singulating trenches is performed using back end of line processing technology.

3. The method as in claim 1 , wherein etching the singulating trenches further comprises:

etching holes in the area of the at least one chip.

4. The method as in claim 1 , further comprising:

performing damascene processing for the back end of line.

5. The method as claim 1 , wherein etching the singulating trenches further comprises:

etching the singulating trenches using a mask with a pattern.

6. The method as in claim 5 , wherein the pattern corresponds to dies with rounded corners.

7. The method as in claim 1 , wherein the back end of line comprises moisture sensitive material.

8. The method as in claim 1 , wherein the stack of layers further comprises a metallization layer between the front end of line and the back end of line.

9. The method as in claim 1 , wherein the passivation layer comprises multiple sublayers.

10. The method as in claim 1 , wherein the depositing is one of physical vapor depositing, chemical vapor depositing and spinning on.

11. The method as in claim 1 , further comprising:

attaching the stack of layers to an adhesive film or foil.

12. The method as in claim 1 , wherein the substrate layer is one of a silicon substrate, a gallium arsenide substrate and a germanium substrate.

13. The method as in claim 1 , wherein the reducing is one of chemical mechanical polishing, grinding and substrate etch backing.

14. A method of singulating at least one chip from a stack of layers, the stack comprising a front end of line upon a substrate layer, the substrate layer having a first surface and a second surface, the front end of line being positioned on top of the first surface, and a back end of line on top of the front end of line, the method comprising:

positioning metal dummies in the back end of line, wherein the metal dummies are positioned outside a chip area and outside an exclusion zone, the exclusion zone surrounding the at least one chip; and

etching singulating trenches through the back end of line, through the front end of line and at least partially through the substrate layer of the stack, wherein the etching is done in the exclusion zone and the singulating trenches surround the at least one chip.

15. The method as in claim 14 , further comprising:

depositing a passivation layer on the stack provided with the etched singulating trenches, such that sidewalls of the trenches are at least partially passivated.

16. The method as in claim 14 , further comprising:

releasing the at least one chip from the stack of layers.

17. The method as in claim 16 , wherein the releasing comprises:

reducing the thickness of the substrate layer from the second surface onwards to the bottom of the etched singulating trenches until the at least one chip is released from the stack.

18. The method as in claim 14 , wherein etching the singulating trenches is performed using back end of line processing technology.

19. The method as in claim 14 , wherein etching the singulating trenches further comprises:

etching holes in the area of the at least one chip.

20. The method as in claim 17 , further comprising:

performing damascene processing for the back end of line.

21. The method as claim 14 , wherein etching the singulating trenches further comprises:

etching the singulating trenches using a mask with a pattern.

22. The method as in claim 21 , wherein the pattern corresponds to dies with rounded corners.

23. The method as in claim 14 , wherein the back end of line comprises moisture sensitive material.

24. The method as in claim 14 , wherein the stack of layers further comprises a metallization layer between the front end of line and the back end of line.

25. The method as in claim 15 , wherein the passivation layer comprises multiple sublayers.

26. The method as in claim 15 , wherein the depositing is one of physical vapor depositing, chemical vapor depositing and spinning on.

27. The method as in claim 14 , further comprising:

attaching the stack of layers to an adhesive film or foil.

28. The method as in claim 14 , wherein the substrate layer is one of a silicon substrate, a gallium arsenide substrate and a germanium substrate.

29. The method as in claim 17 , wherein the reducing is one of chemical mechanical polishing, grinding and substrate etch backing.

30. The method of claim 1 , comprising depositing the passivation layer on the stack provided with the etched singulating trenches, such that sidewalls of the front end of line and the back end of line are substantially passivated.