IP Library Granted Patent US 7,138,935
Granted Patent B1
US 7,138,935 · App. 11/236,205 · Granted Nov 21, 2006

Low noise digital to signal interval converter with audio applications

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Quick Facts
Patent No.
US 7,138,935
App. No.
11/236,205
Granted
Nov 21, 2006
Kind
B1
Abstract

The present invention relates to digital-to-analog conversion. In particular, it has application to conversion of pulse code modulated signals, such as used in CDs and DVDs, to a pulse width modulated or analog signal.

Claims (32)

1. A method of converting a wide-bit digital input signal into a digital signal with a fixed frequency of rising edges, the method including:

oversampling a wide-bit input signal to one-bit samples;

processing a number S of samples from the oversampling, the number S corresponding to an output signal precision;

determining proportions of high and low signal values among the S samples; and

outputting a signal interval having a fixed frequency of rising edges, proportions of the signal interval at high and low signal values corresponding to the determined proportions of high and low signal values among the S samples.

2. The method of claim 1 , further including

digitally filtering a stream of the signal intervals, the digital filter

producing a correction signal that at least partially compensates for distortion introduced translating the S samples to a signal interval and

formatting the correction signal to match precision and frequency of the wide-bit input signal; and

combining the formatted correction signal with a version of the wide-bit input to produce a corrected signal.

3. The method of claim 2 , further including feeding back the formatted correction signal to the wide-bit input and integrating a resulting difference value with at least one earlier wide-bit input.

4. The method of claim 2 , wherein there is has a single transition between high and low signal values within the signal interval.

5. An integrated circuit including logic and resources adapted to carry out the method of claim 1 .

6. A machine readable memory impressed with instructions to carry out the method of claim 1 .

7. A machine readable memory impressed with instructions to produce an integrated circuit having logic and resources adapted to carry out the method of claim 1 .

8. A method of converting a wide-bit digital input signal into a digital signal with a fixed frequency of rising edges, the method including:

oversampling a wide-bit input to produce samples;

generating a base signal that has at least one place holder for receiving a value from one of the samples, the base signal producing a fixed frequency of rising edges, regardless of the value;

filling the place holder with the value; and

outputting a resulting signal with a fixed frequency of rising edges.

9. The method of claim 8 , wherein the base signal has one high signal value and one low signal value with the placeholder in between the high and the low signal values.

10. The method of claim 8 , wherein the base signal has one high signal value, one low signal value and two placeholders in a pattern (x1y2) of first signal value-first place holder-second signal value-second place holder.

11. The method of claim 8 , wherein the base signal has two high signal values, two low signal values and two placeholders in a pattern (x1yy2x) of first signal value-first place holder-second signal value-second signal value-second place holder-first place holder.

12. The method of claim 8 , further including:

digitally filtering a stream of the resulting signals, the digital filter

producing a correction signal that at least partially compensates for distortion introduced by combining the values with the base signal and

formatting the correction signal to match precision and frequency of the wide-bit input signal; and

combining the formatted correction signal with a version of the wide-bit input to produce a corrected signal.

13. The method of claim 12 , further including feeding back the formatted correction signal to the wide-bit input and integrating a resulting difference value with at least one earlier wide-bit input.

14. An integrated circuit including logic and resources adapted to carry out the method of claim 8 .

15. A machine readable memory impressed with instructions to carry out the method of claim 8 .

16. A machine readable memory impressed with instructions to produce an integrated circuit having logic and resources adapted to carry out the method of claim 8 .

Assignments (2)
SECURITY AGREEMENT Recorded Jul 9, 2008
From: ESS TECHNOLOGY, INC.
To: THE PRIVATE BANK OF THE PENINSULA
Reel/Frame 021212/0413 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2005
From: DAMPHOUSSE, SIMON; MALLINSON, A. MARTIN; FORMAN, DUSTIN D.
To: ESS TECHNOLOGY, INC.
Reel/Frame 017354/0894 →