Enhanced passive optical network (PON) processor
View Patent ↗An enhanced passive optical network (PON) processor adapted to serve a plurality of PON applications is disclosed. The PON processor is a highly integrated communications processor that can operate in different PON modes including, but not limited to, a gigabit PON (GPON), a broadband PON (BPON), an Ethernet PON (EPON), or any combination thereof. In an embodiment of the present invention the provided PON is fabricated on a single integrated circuit (IC).
1. An enhanced passive optical network (PON) processor adapted to operate in a plurality of PON operating modes, said PON processor comprising:
a microprocessor;
a packet processor for processing PON traffic and being coupled to said microprocessor for providing instructions thereto;
an Ethernet media access control (MAC) adapter coupled to the packet processor for interfacing with a plurality of subscriber devices; and
a PON MAC adapter coupled to the packet processor for serving a multi-service optical network unit (ONU) of the PON by handling data flows a plurality of PON operating modes and comprising a Gigabit PON (GPON) MAC adapter, a broadband PON (BPON) MAC adapter, and an Ethernet PON (EPON) adapter.
2. The enhanced PON processor of claim 1 , further comprising:
a system integration unit (SIU) for forwarding interface and control signals to said microprocessor and said packet processor;
a broad bus coupled to said packet processor, said Ethernet MAC adapter, and said PON MAC adapter;
a serial-deserial (SERDES) unit for deserializing a downstream PON traffic received and serializing an upstream PON traffic;
a memory controller for interfacing with an external memory; and
an internal bus for inter-connecting between said SIU, said microprocessor, and said packet processor.
3. The enhanced PON processor of claim 1 , wherein said microprocessor is capable of handling multiple processing tasks with a task switch in a single clock.
4. The enhanced PON processor of claim 1 , wherein said plurality of PON operating modes include at least: a Gigabit PON (GPON) mode, a broadband PON (BPON) mode, and an Ethernet PON (EPON).
5. The enhanced PON processor of claim 1 , wherein said Ethernet MAC adapter comprises a plurality of Ethernet interfaces for receiving upstream data flows from said subscriber devices and transmitting downstream data flows to subscriber devices.
6. The enhanced PON processor of claim 5 , wherein each of said Ethernet interfaces includes at least one of: a 100 Mbit Ethernet interface, a 1 Gigabit Ethernet interface.
7. The enhanced PON processor of claim 1 , wherein the processing tasks carried by said packet processor include: filtering, forwarding-and-learning, queuing packets, shaping packets, flow classification, packets classification, reassembling of packets.
8. The enhanced PON processor of claim 1 , wherein said packet processor comprising at least: a core processor; a plurality of hardware (HW) accelerators; and a memory unit.
9. The enhanced PON processor of claim 8 , wherein said plurality of hardware (HW) accelerators include: a lookup table, a cyclical redundancy checking (CRC) accelerator, a scheduler, a register file, a direct memory access (DMA), and a board bus interface.
10. The enhanced PON processor of claim 8 , wherein said memory unit includes: a data memory, a context memory, and a program memory.
11. The enhanced PON processor of claim 1 , wherein said enhanced PON processor is fabricated on a single integrated circuit (IC).
12. The enhanced PON processor of claim 1 , wherein said PON traffic comprises a PON upstream traffic and a PON downstream traffic, wherein said PON upstream traffic and a PON downstream traffic are processed according to a respective PON mode.
13. The enhanced PON processor of claim 12 , wherein the processing of said PON downstream traffic comprises:
receiving at said PON MAC adapter data chunks of data packets sent from an optical line terminal (OLT) of an optical network;
reassembling said data chunks into packets by said packet processor; and
forwarding said reassembled packets to the subscriber devices through said Ethernet MAC adapter.
14. The enhanced PON processor of claim 13 , being further adapted to perform correctness checks of said reassembled packets.
15. The enhanced PON processor of claim 14 , wherein the correctness checks include at least one of: a cyclical redundancy checking (CRC) check, a flow validity check.
16. The enhanced PON processor of claim 13 , wherein the processing of said PON upstream comprises:
receiving at said Ethernet MAC adapter data chunks of Ethernet frames sent from said subscriber devices;
reassembling said data chunks into packets by said packet processor;
sending reassembled packets to said PON MAC adapter; and
upon receiving a grant from an OLT, transmitting said reassembled packets to said OLT.
17. The enhanced PON processor of claim 16 , wherein the PON MAC adapter maintains said reassembled packets in traffic containers (T-CONTs).
18. The enhanced PON processor of claim 17 , wherein the grant is per T-CONT.