Signal line, a thin film transistor array panel comprising the signal line, and method for manufacturing the same
View Patent ↗A thin film transistor array panel includes an insulating substrate, a gate line formed on the insulating substrate, a gate insulating layer formed on the gate line, a drain electrode and a data line having a source electrode formed on the gate insulating layer wherein the drain electrode faces the source electrode with a gap therebetween, and a pixel electrode connected to the drain electrode. At least one of the gate line, the data line, and the drain electrode includes a first conductive layer made of a conductive oxide and a second conductive layer of Ag that is deposited adjacent to the first conductive layer.
1. A signal line for a display device comprising:
a signal line having:
a first conductive layer;
a second conductive layer formed on the first conductive layer and containing Ag; and
a third conductive layer formed on the second conductive layer;
wherein the first conductive layer and the third conductive layer comprise a nitrogenated conductive oxide.
2. The signal line for a display device of claim 1 , wherein the first conductive layer and the third conductive layer comprise an ITON or IZON.
3. The signal line for a display device of claim 2 , wherein the first conductive oxide and the third conductive oxide are in a crystallized state.
4. A thin film transistor array panel comprising:
an insulating substrate;
a gate line formed on the insulating substrate;
a gate insulating layer formed on the gate line;
a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode facing the source electrode with a gap therebetween; and
a pixel electrode connected to the drain electrode,
wherein at least one of the gate line, the data line, and the drain electrode includes a first conductive layer, second conductive layer formed on the first conductive layer and containing Ag, and a third conductive layer deposited on the second conductive layer;
wherein the second conductive layer is thicker than the first conductive layer and the third conductive layer; and
wherein the first conductive layer and the third conductive layer are made of a conductive oxide.
5. The thin film transistor array panel of claim 4 , wherein the first conductive layer and the third conductive layer are made of an indium oxide.
6. The thin film transistor array panel of claim 5 , wherein the indium oxide is one of ITO or IZO.
7. The thin film transistor array panel of claim 6 , wherein the indium oxide is one of ITON or IZON.
8. The thin film transistor array panel of claim 4 , wherein the first conductive layer and the third conductive layer are in a crystallized state.
9. The thin film transistor array panel of claim 4 , wherein the first conductive layer and the third conductive layer have a thickness of about 30 to about 300 Å.
10. The thin film transistor array panel of claim 9 , wherein the second conductive layer has a thickness of about 1,000 to about 3,000 Å.