High-density germanium-on-insulator photodiode array

1. A method for forming a high-density Germanium (Ge)-n-Insulator (GOI) photodiode array, the method comprising:

forming an array of pixel driver nMOST devices, each device having a gate connected to a row line in a first orientation, a first source/drain (S/D) region, and a second S/D region connected to Vdd;

forming a P-I-N Ge diode for each pixel as follows:

forming a n+ region;

forming an intrinsic Ge region overlying the n+ region;

forming a p+ junction in the intrinsic Ge region; and,

isolating the P-I-N Ge diodes; and,

forming an Indium Tin oxide (ITO) column in a second orientation, about orthogonal to the first orientation, overlying the P-I-N Ge diodes.

2. The method of claim 1 wherein forming the n+ region includes:

forming a planarized layer of oxide overlying the nMOST device, with a top surface;

forming a contact hole through the planarized oxide to the first S/D region; and,

epitaxially growing Ge in the contact hole.

3. The method of claim 2 wherein epitaxially growing Ge in the contact hole includes a using a process selected from the group including:

selectively growing n+ doped Ge in the contact hole; and

growing intrinsic Ge, followed by an n+ ion implantation.

4. The method of claim 2 wherein forming the n+ region includes:

depositing an amorphous Ge layer overlying the planarized oxide top surface, having a thickness in the range of about 10 to 30 nanometers (nm);

implanting Antimony (Sb) with an energy in the range of about 20 keV to about 50 keV, at a dose in the range of about 2×10 13 to about 1×10 15 per square centimeter (/cm 2 );

followed by an etching to form contact holes through the planarized oxide to the first S/D region.

5. The method of claim 2 wherein forming the n+ region includes a using a process selected from the group comprising:

implanting Sb into the planarized oxide with an energy in the range of about 20 keV to about 50 keV, at a dose in the range of about 2×10 13 to about 1×10 15 /cm 2 ; and,

depositing a heavily Sb-doped oxide (NSG) overlying the planarized oxide top surface, having a thickness in the range of about 50 to 100 nm;

followed by an etching to form contact holes through the planarized oxide to the first S/D region.

6. The method of claim 2 further comprising:

depositing a Silicon nitride (SiN) placeholder, having a thickness in the range of about 500 to 3000 nm, overlying the n+ region;

wherein isolating the P-I-N Ge diodes includes:

selectively etching the SiN placeholder and the n+ region to form an isolation trench; and,

filling the isolation trench with oxide;

wherein forming the intrinsic Ge region overlying the n+ region further includes:

etching to remove the SiN placeholder; and,

epitaxially growing Ge from the n+ region.

7. The method of claim 1 wherein forming the intrinsic Ge region overlying the n+ region includes depositing amorphous Ge having a thickness in the range of about 500 to 3000 nm.

8. The method of claim 7 wherein isolating the P-I-N Ge diodes includes:

depositing a SiN cap overlying the amorphous Ge, having a thickness in the range of about 10 to 50 nm;

selectively etching the SiN cap, amorphous Ge, and n+ region, forming an isolation trench;

filling the isolation trench with oxide;

rapid thermal annealing; and,

etching to remove the SiN cap.

9. The method of claim 1 wherein forming the p+ junction in the intrinsic Ge region includes:

implanting Indium with an energy in the range of about 30 to 50 keV, at a dose in the range of about 5×10 13 to about 1×10 15 /cm 2 ; and,

annealing at a temperature in the range of about 500 to 800° C., for a time duration in the range of about 10 second to about 10 minutes.

10. The method of claim 1 wherein isolating the P-I-N Ge diodes includes forming an isolation trench having a width equal to the minimum feature size of the photodiode array fabrication process.

11. A method for forming a high-density Germanium (Ge)-on-Insulator (GOI) photodiode array, the method comprising:

forming an array of pixel driver pMOST devices, each device having a gate connected to a row line in a first orientation, a first source/drain (S/D) region, and a second S/D region connected to Vdd;

forming a N-I-P Ge diode for each pixel as follows:

forming a p+ region;

forming an intrinsic Ge region overlying the p+ region;

forming a n+ junction in the intrinsic Ge region; and,

isolating the N-I-P Ge diodes; and,

forming an Indium Tin oxide (ITO) column in a second orientation, about orthogonal to the first orientation, overlying the N-I-P Ge diodes.

12. A high-density Germanium (Ge)-on-Insulator (GOI) photodiode array, the array comprising:

a first plurality of pixel driver nMOST devices with gates connected to a second plurality of row lines in a first orientation, each device having a first source/drain (S/D) region, and a second S/D region connected to Vdd;

a first plurality of P-I-N Ge diodes, each diode comprising:

an n+ Ge via overlying the first S/D region of a corresponding device;

an n+ layer overlying the n+ Ge via;

an intrinsic Ge layer overlying the n+ layer;

a p+ Ge layer overlying the intrinsic Ge layer; and,

a third plurality of Indium Tin oxide (ITO) columns in a second orientation, about orthogonal to the first orientation, overlying the P-I-N Ge diodes in the second plurality of row lines.

13. The array of claim 12 further comprising:

a planarized layer of oxide overlying the nMOST device, with a top surface;

wherein the n+ Ge via is formed in a contact hole from the planarized oxide top surface to the first S/D region; and,

wherein the n+ Ge via is epitaxially grown Ge.

14. The array of claim 13 wherein the n+ layer is selected from the group comprising:

an Antimony (Sb)-doped Ge layer with a thickness of about 10 to 30 nanometers (nm);

a Sb-doped Silicon oxide (NSG) layer with a thickness of about 50 to 100 nm; and,

a planarized oxide layer implanted with Sb having a thickness of about 0.01 to 0.05 micrometers; and,

wherein the array further comprises:

an n+ via interposed between the first S/D region and the n+ layer.

15. The array of claim 12 wherein the intrinsic Ge layer has a thickness in the range of about 500 to 3000 nm.

16. The array of claim 12 wherein the intrinsic Ge layer is a material selected from the group comprising amorphous Ge and epitaxially grown Ge.

17. The array of claim 12 further comprising:

a Silicon oxide-filled isolation trench separating adjacent P-I-N diodes.

18. The array of claim 17 wherein the isolation trench has a trench width equal to the minimum feature size of the photodiode array fabrication process.

19. A high-density Germanium (Ge)-on-Insulator (GOI) photodiode array, the array comprising:

a first plurality of pixel driver pMOST devices with gates connected to a second plurality of row lines in a first orientation, each device having a first source/drain (S/D) region, and a second S/D region connected to Vdd;

a first plurality of N-I-P Ge diodes, each diode comprising:

a p+ Ge via overlying the first S/D region of a corresponding device;

a p+ layer overlying the p+ Ge via;

an intrinsic Ge layer overlying the p+ layer;

an n+ Ge layer overlying the intrinsic Ge layer; and,

a third plurality of Indium Tin oxide (ITO) columns in a second orientation, about orthogonal to the first orientation, overlying the P-I-N Ge diodes in the second plurality of row lines.