Reliable transceiver microcode update mechanism
View Patent ↗A method for dynamically updating an optical transceiver (or optical transmitter or optical receiver) that has at least one processor, a persistent memory, and a microcode loader mechanism. The persistent memory includes microcode comprising instructions that, when executed by the at least one processor, control at least one component of the optical transceiver, transmitter, or receiver. In order to implement the invention, data is written to the persistent memory of the optical transceiver to indicate that an updating of microcode currently stored on the persistent memory is to occur. The optical transceiver processes received microcode, which contains instructions that are structured such that when executed by the at least one processor of the optical transceiver, the execution of the instructions affects the operation of the optical transceiver. Then, the processed representation of the received microcode is written to the persistent memory. The optical transceiver then determines that all of the microcode that is to be written to the persistent memory during the update has been written to the persistent memory. Finally, the persistent memory is altered to reflect that the update is complete.
1. A method for dynamically updating an optical transceiver that includes at least one processor and a persistent memory, the method comprising the following:
an act of the optical transceiver writing data to the persistent memory of the optical transceiver to indicate that an updating of microcode currently stored on the persistent memory is to occur;
an act of the optical transceiver processing received microcode containing instructions that are structured such that when executed by the at least one processor of the optical transceiver, the execution of the instructions affects the operation of the optical transceiver, wherein the microcode includes operational or control code in the form of firmware and/or software that runs on the at least one processor and controls the operation of the optical transceiver when executed;
an act of the optical transceiver causing at least the processed representation of the received microcode to be written to the persistent memory;
an act of the optical transceiver determining that all of the microcode that is to be written to the persistent memory during the update has been written to the persistent memory; and
an act of the optical transceiver altering persistent memory to reflect that the update is complete.
2. A method as recited in claim 1 , wherein the received microcode is structured to support a temperature compensation for a different range of temperatures as compared to the microcode currently stored on the persistent memory.
3. A method as recited in claim 1 , wherein the received microcode is structured to support operations for a different range of receive power as compared to the microcode currently stored on the persistent memory.
4. A method as recited in claim 1 , further comprising: an act of the optical transceiver receiving microcode from a host computing system; and preventing the optical transmitter from transmitting while the microcode is executed by the one or more processors.
5. A method as recited in claim 4 , wherein the received microcode is received from the host computing system over a network.
6. A method as recited in claim 4 , wherein the received microcode is received from the host computing system over the Internet.
7. A method as recited in claim 1 , wherein the act of the optical transceiver processing received microcode includes transferring the received microcode to the persistent memory.
8. A method as recited in claim 1 , wherein the act of the optical transceiver processing received microcode includes decrypting the received microcode.
9. A method as recited in claim 1 , wherein the act of the optical transceiver processing received microcode includes decompressing the received microcode.
10. An optical transmitter comprising:
at least one processor;
a persistent memory having thereon microcode comprising instructions that, when executed by the at least one processor, control at least one component of the optical transmitter, wherein the persistent memory is coupled to the at least one processor such that the processor may read and execute the microcode; and
a microcode loader mechanism configured to perform the following:
write data to the persistent memory of the optical transmitter to indicate that an updating of the microcode on the persistent memory is to occur;
receive updated microcode, wherein the microcode includes operational or control code in the form of firmware and/or software that runs on the at least one processor and controls the operation of the optical transceiver when executed;
write the updated microcode to the persistent memory during the microcode update; and
alter the persistent memory to reflect that the update is complete upon completion of the microcode update.
11. An optical transmitter as recited in claim 10 , wherein the updated microcode is structured to support a temperature compensation for a predetermined range of temperatures.
12. An optical transmitter as recited in claim 10 , wherein the updated microcode is structured to support operations for a predetermined range of receive power.
13. An optical transmitter as recited in claim 10 , further comprising an interface to a host computing system, wherein the host computing system sends the updated microcode to the optical transmitter.
14. An optical transmitter as recited in claim 13 , wherein the updated microcode is received from the host computing system over a network.
15. An optical transmitter as recited in claim 13 , wherein the updated microcode is received from the host computing system over the Internet.
16. An optical transmitter as recited in claim 10 , wherein the persistent memory includes one or more write-protected memory locations.
17. An optical transmitter as recited in claim 10 , wherein at least one of the write-protected memory locations stores a loader microcode for execution when the optical transceiver is to perform the microcode update.
18. An optical transmitter as recited in claim 10 , wherein the optical transmitter is a portion of an optical transceiver.
19. An optical receiver comprising:
at least one processor;
a persistent memory having thereon microcode comprising instructions that, when executed by the at least one processor, control at least one component of the optical receiver, wherein the persistent memory is coupled to the at least one processor such that the processor may read and execute the microcode; and
a microcode loader mechanism configured to perform the following:
write data to the persistent memory of the optical transmitter to indicate that an updating of the microcode on the persistent memory is to occur;
receive updated microcode, wherein the microcode includes operational or control code in the form of firmware and/or software that runs on the at least one processor and controls the operation of the optical transceiver when executed;
write the updated microcode to the persistent memory during the microcode update; and
alter the persistent memory to reflect that the update is complete upon completion of the microcode update.
20. An optical receiver as recited in claim 19 , further comprising: a system memory for storing the updated microcode upon the reception of the updated microcode, wherein during the microcode update, the updated microcode is read from the system memory and written to the persistent memory.