Thin film transistor array panel and manufacturing method thereof
View Patent ↗A thin film transistor array panel according to an embodiment includes: a substrate; a plurality of gate line formed on the substrate; a plurality of first capacitor electrodes formed on the substrate and separated from the gate lines; a plurality of data line intersecting the gate lines; a plurality of thin film transistor connected to the gate lines and the data lines; a plurality of second capacitor electrodes disposed on the first electrode; a plurality of interconnections connected to the second capacitor electrodes and the thin film transistor and disposed symmetrical to the data lines; and a plurality of pixel electrode, each pixel electrode including a first subpixel electrode connected to one of the thin film transistors and a second subpixel electrode connected to one of the first capacitor electrodes.
1. A liquid crystal display, comprising:
a first substrate;
a gate line formed on the first substrate;
a first capacitor electrode formed on the substrate and separated from the gate line;
a data line intersecting the gate line;
a thin film transistor connected to the gate line and the data line;
a second capacitor electrode disposed on the first capacitor electrode;
a plurality of first electrodes connected to the second capacitor electrode and the thin film transistor and disposed substantially symmetrical to the data line;
a pixel electrode including at least one first subpixel electrode connected to the thin film transistor and a second subpixel electrode connected to the first capacitor electrode;
a second substrate facing the first substrate; and
a common electrode formed on the second substrate.
2. The liquid crystal display of claim 1 , wherein the first electrode is substantially parallel with the date line and the distance between the first electrode and the data line is smaller than about 42 microns.
3. The liquid crystal display of claim 2 , further comprising:
at least one structural member connected to the thin film transistor; and
at least one storage electrode overlapping the at least one structural member.
4. The liquid crystal display of claim 3 , wherein the at least one first subpixel electrode comprises a third subpixel electrode and a fourth subpixel electrode.
5. The liquid crystal display of claim 4 , wherein the at least one structural member comprises first and second structural members connected to the third and the fourth subpixel electrodes, respectively, and disposed substantially symmetrical to a reference line bisecting the pixel electrode and extending parallel to the gate line.
6. The liquid crystal display of claim 5 , wherein the at least one storage electrode comprises first and second storage electrodes overlapping the first and the second structural members, respectively.
7. The liquid crystal display of claim 6 , wherein the first electrodes are disposed substantially symmetrical to the reference line.
8. The liquid crystal display of claim 5 , wherein the pixel electrode is substantially symmetrical to the reference line.
9. The liquid crystal display of claim 2 , wherein the pixel electrode overlaps the first electrodes.
10. The liquid crystal display of claim 2 , wherein the first electrodes overlap the first capacitor electrode.
11. The liquid crystal display of claim 1 , wherein the second capacitor electrode has a through-hole, and the second subpixel electrode and the first capacitor electrode are connected to each other through the through-hole.
12. The liquid crystal display of claim 1 , wherein one of the first capacitor electrode and the second capacitor electrode is disposed substantially symmetrical to a reference line bisecting the pixel electrode and parallel to the gate line.
13. The liquid crystal display of claim 1 , further comprising a shielding electrode separated from the pixel electrode and overlapping a predetermined portion of one of the data line and the gate line.
14. The liquid crystal display of claim 13 , wherein the pixel electrode and the shielding electrode comprise the same layer.
15. The liquid crystal display of claim 14 , wherein the shielding electrode extends along one of the data line and the gate line.
16. The liquid crystal display of claim 15 , wherein the shielding electrode fully covers the data line.
17. The liquid crystal display of claim 1 , wherein at least one of the first subpixel electrode and the second subpixel electrode has a partitioning member for partitioning the pixel electrode into a plurality of domains.
18. The liquid crystal display of claim 17 , wherein the partitioning member is elongated and is disposed at an angle of about 45 degrees with the gate line.
19. The liquid crystal display of claim 1 , wherein the pixel electrode overlaps the first electrodes.
20. The liquid crystal display of claim 1 , wherein the first electrodes overlap the first electrode.