Mode-selecting apparatus, display apparatus including the same, and method of selecting a mode in display unit

1. A mode-selecting apparatus for selecting one of a first mode in which images are displayed on a display unit in accordance with a vertical synchronization control signal and a horizontal synchronization control signal, and a second mode in which images are displayed on said display unit in accordance with a data-enable signal, including:

a first unit which counts a number of input horizontal synchronization control signals in each of frame periods;

a second unit which counts a number of input data-enable signals in each of frame periods; and

a third unit which selects one of said first and second modes in accordance with both said number of input horizontal synchronization control signals and said number of input data-enable signals,

wherein said first unit resets said number of input horizontal synchronization control signals, and said second unit resets said number of input data-enable signals,

wherein said first unit detects a first timing at which said number of input horizontal synchronization control signals is equal to M wherein M indicates a predetermined positive integer, and said second unit detects a second timing at which said number of input data-enable signals is equal to N wherein N indicates a predetermined positive integer smaller than said M, and

wherein said third unit selects said first mode if said number of input data-enable signals is equal to zero (0) at an earlier timing among said first and second timings, and selects said second mode if said number of input data-enable signals is not equal to zero (0) at an earlier timing among said first and second timings.

2. The mode-selecting apparatus as set forth in claim 1 , wherein said first unit produces a first target-arrival signal at said first timing, and said second unit produces a second target-arrival signal at said second timing, and further including a fourth unit which produces a logical-sum signal at a timing at which at least one of said first and second target-arrival signal is produced,

and wherein said third unit selects said first mode if said number of input data-enable signals is equal to zero (0) at a timing at which said logical-sum signal is produced, and selects said second mode if said number of input data-enable signals is not equal to zero (0) at a timing at which said logical-sum signal is produced.

3. The mode-selecting apparatus as set forth in claim 2 , wherein said first unit resets said first target-arrival signal, and said second unit resets said second target-arrival signal.

4. The mode-selecting apparatus as set forth in claim 3 , wherein said first unit resets said first target-arrival signal at a timing at which each of frame periods ends, and said second unit resets said second target-arrival signal at a timing at which each of frame periods ends.

5. The mode-selecting apparatus as set forth in claim 4 , wherein said timing is defined by one of a second signal having a frame period and produced in accordance with said data-enable signals, and said vertical synchronization control signals.

6. The mode-selecting apparatus as set forth in claim 5 , wherein said timing is an earlier timing among a timing at which said second signal falls down, and a timing at which said vertical synchronization control signal falls down.

7. The mode-selecting apparatus as set forth in claim 1 , wherein said N is greater than a maximum number of said horizontal synchronization control signals which can be input thereinto in a non-display period in each of frame periods.

8. A mode-selecting apparatus for selecting one of a first mode in which images are displayed on a display unit in accordance with a vertical synchronization control signal and a horizontal synchronization control signal, and a second mode in which images are displayed on said display unit in accordance with a data-enable signal, including:

a first unit which counts a number of input horizontal synchronization control signals, and resets said number of input horizontal synchronization control signals;

a second unit which counts a number of input data-enable signals, and resets said number of input data-enable signals; and

a third unit which selects one of said first and second modes in accordance with both said number of input horizontal synchronization control signals and said number of input data-enable signals,

wherein said first unit detects a first timing at which said number of input horizontal synchronization control signals is equal to M wherein M indicates a predetermined positive integer, and said second unit detects a second timing at which said number of input data-enable signals is equal to N wherein N indicates a predetermined positive integer smaller than said M,

and wherein said third unit selects said first mode if said number of input data-enable signals is equal to zero (0) at an earlier timing among said first and second timings, and selects said second mode if said number of input data-enable signals is not equal to zero (0) at an earlier timing among said first and second timings.

9. The mode-selecting apparatus as set forth in claim 8 , wherein said first unit produces a first target-arrival signal at said first timing, and said second unit produces a second target-arrival signal at said second timing, and further including a fourth unit which produces a logical-sum signal at a timing at which at least one of said first and second target-arrival signal is produced,

and wherein said third unit selects said first mode if said number of input data-enable signals is equal to zero (0) at a timing at which said logical-sum signal is produced, and selects said second mode if said number of input data-enable signals is not equal to zero (0) at a timing at which said logical-sum signal is produced.

10. The mode-selecting apparatus as set forth in claim 9 , wherein said first unit resets said first target-arrival signal, and said second unit resets said second target-arrival signal.

11. The mode-selecting apparatus as set forth in claim 10 , wherein said first unit resets said first target-arrival signal at a timing at which each of frame periods ends, and said second unit resets said second target-arrival signal at a timing at which each of frame periods ends.

12. The mode-selecting apparatus as set forth in claim 11 , wherein said timing is defined by one of a second signal having a frame period and produced in accordance with said data-enable signals, and said vertical synchronization control signals.

13. The mode-selecting apparatus as set forth in claim 12 , wherein said timing is an earlier timing among a timing at which said second signal falls down, and a timing at which said vertical synchronization control signal falls down.

14. The mode-selecting apparatus as set forth in claim 8 , wherein said N is greater than a maximum number of said horizontal synchronization control signals which can be input thereinto in a non-display period in each of frame periods.

15. A mode-selecting apparatus for selecting one of a first mode in which images are displayed on a display unit in accordance with a vertical synchronization control signal and a horizontal synchronization control signal, and a second mode in which images are displayed on said display unit in accordance with a data-enable signal, including:

a first unit which (a) counts a number of input horizontal synchronization control signals, (b) resets said number of input horizontal synchronization control signals at each of a timing at which a n-VALID signal having a frame period and produced in accordance with said data-enable signal rises up, and a timing at which said vertical synchronization control signal rises up, (c) produces a HC-RC signal designed to be in a high level at a first timing at which said number of input horizontal synchronization control signals is equal to M wherein M indicates a predetermined positive integer, and (d) resets said HC-RC signal into a low level at an earlier timing among a timing at which said n-VALID signal falls down, and a timing at which said vertical synchronization control signal falls down;

a second unit which (a) counts a number of input data-enable signals, (b) resets said number of input data-enable signals at each of a timing at which a signal having a frame period and produced in accordance with said data-enable signal rises up, and a timing at which said vertical synchronization control signal rises up, (c) produces a DC-RC signal designed to be in a high level at a second timing at which said number of input data-enable signals is equal to N wherein N indicates a predetermined positive integer smaller than said M, and (d) resets said DC-RC signal into a low level at an earlier timing among a timing at which said n-VALID signal falls down, and a timing at which said vertical synchronization control signal falls down;

a third unit which selects one of said first and second modes; and

a fourth unit which produces a logical-sum signal designed to be in a high level at a timing at which at least one of said HC-RC signal and said DC-RC signal is in a high level,

said third unit selecting said first mode if said number of input data-enable signals is equal to zero (0) at a timing at which said logical-sum signal was produced, and selecting said second mode if said number of input data-enable signals is not equal to zero (0) at said timing.

16. The mode-selecting apparatus as set forth in claim 15 , wherein said N is greater than a maximum number of said horizontal synchronization control signals which can be input thereinto in a non-display period in each of frame periods.

17. The mode-selecting apparatus as set forth in claim 15 , wherein said first and second units re-count said number of input horizontal synchronization control signals and said number of said input data-enable signals, starting from zero (0), after said number of input horizontal synchronization control signals and said number of said input data-enable signals reached maximum numbers countable by said first and second units.

18. A display apparatus including:

a display unit; and

a mode-selecting apparatus for selecting one of a first mode in which images are displayed on said display unit in accordance with a vertical synchronization control signal and a horizontal synchronization control signal, and a second mode in which images are displayed on said display unit in accordance with a data-enable signal, including:

a first unit which (a) counts a number of input horizontal synchronization control signals, (b) resets said number of input horizontal synchronization control signals at each of a timing at which a n-VALID signal having a frame period and produced in accordance with said data-enable signal rises up, and a timing at which said vertical synchronization control signal rises up, (c) produces a HC-RC signal designed to be in a high level at a first timing at which said number of input horizontal synchronization control signals is equal to M wherein M indicates a predetermined positive integer, and (d) resets said HC-RC signal into a low level at an earlier timing among a timing at which said n-VALID signal falls down, and a timing at which said vertical synchronization control signal falls down;

a second unit which (a) counts a number of input data-enable signals, (b) resets said number of input data-enable signals at each of a timing at which a signal having a frame period and produced in accordance with said data-enable signal rises up, and a timing at which said vertical synchronization control signal rises up, (c) produces a DC-RC signal designed to be in a high level at a second timing at which said number of input data-enable signals is equal to N wherein N indicates a predetermined positive integer smaller than said M, and (d) resets said DC-RC signal into a low level at an earlier timing among a timing at which said n-VALID signal falls down, and a timing at which said vertical synchronization control signal falls down;

a third unit which selects one of said first and second modes; and

a fourth unit which produces a logical-sum signal designed to be in a high level at a timing at which at least one of said HC-RC signal and said DC-RC signal is in a high level,

said third unit selecting said first mode if said number of input data-enable signals is equal to zero (0) at a timing at which said logical-sum signal was produced, and selecting said second mode if said number of input data-enable signals is not equal to zero (0) at said timing.

19. The display apparatus as set forth in claim 18 , wherein said display apparatus is comprised of a liquid crystal display unit including a liquid crystal display panel as said display unit.

20. A method of selecting one of a first mode in which images are displayed on a display unit in accordance with a vertical synchronization control signal and a horizontal synchronization control signal, and a second mode in which images are displayed on said display unit in accordance with a data-enable signal, including:

counting a number of input horizontal synchronization control signals in each of frame periods;

counting a number of input data-enable signals in each of frame periods;

selecting one of said first and second modes in accordance with both said number of input horizontal synchronization control signals and said number of input data-enable signals,

detecting a first timing at which said number of input horizontal synchronization control signals is equal to M wherein M indicates a predetermined positive integer;

detecting a second timing at which said number of input data-enable signals is equal to N wherein N indicates a predetermined positive integer smaller than said M; and

selecting either said first mode if said number of input data-enable signals is equal to zero (0) at an earlier timing among said first and second timings, or said second mode if said number of input data-enable signals is not equal to zero (0) at an earlier timing among said first and second timings.

21. The method as set forth in claim 20 , further including producing a first target-arrival signal at said first timing, producing a second target-arrival signal at said second timing, producing a logical-sum signal at a timing at which at least one of said first and second target-arrival signal is produced, selecting either said first mode if said number of input data-enable signals is equal to zero (0) at a timing at which said logical-sum signal is produced, or said second mode if said number of input data-enable signals is not equal to zero (0) at a timing at which said logical-sum signal is produced.

22. The method as set forth in claim 21 , further including resetting said first target-arrival signal at a timing at which each of frame periods ends, and resetting said second target-arrival signal at a timing at which each of frame periods ends.

23. A method of selecting one of a first mode in which images are displayed on a display unit in accordance with a vertical synchronization control signal and a horizontal synchronization control signal, and a second mode in which images are displayed on said display unit in accordance with a data-enable signal, including:

counting a number of input horizontal synchronization control signals;

counting a number of input data-enable signals;

resetting said number of input horizontal synchronization control signals;

resetting said number of input data-enable signals;

selecting one of said first and second modes in accordance with both said number of input horizontal synchronization control signals and said number of input data-enable signals;

detecting a first timing at which said number of input horizontal synchronization control signals is equal to M wherein M indicates a predetermined positive integer;

detecting a second timing at which said number of input data-enable signals is equal to N wherein N indicates a predetermined positive integer smaller than said M; and

selecting either said first mode if said number of input data-enable signals is equal to zero (0) at an earlier timing among said first and second timings, or said second mode if said number of input data-enable signals is not equal to zero (0) at an earlier timing among said first and second timings.

24. The method as set forth in claim 23 , further including producing a first target-arrival signal at said first timing, producing a second target-arrival signal at said second timing, producing a logical-sum signal at a timing at which at least one of said first and second target-arrival signal is produced, selecting either said first mode if said number of input data-enable signals is equal to zero (0) at a timing at which said logical-sum signal is produced, or said second mode if said number of input data-enable signals is not equal to zero (0) at a timing at which said logical-sum signal is produced.

25. A method of selecting one of a first mode in which images are displayed on a display unit in accordance with a vertical synchronization control signal and a horizontal synchronization control signal, and a second mode in which images are displayed on said display unit in accordance with a data-enable signal, including:

counting a number of input horizontal synchronization control signals;

counting a number of input data-enable signals;

resetting said number of input horizontal synchronization control signals at each of a timing at which a n-VALID signal having a frame period and produced in accordance with said data-enable signal rises up, and a timing at which said vertical synchronization control signal rises up;

resetting said number of input data-enable signals at each of a timing at which a signal having a frame period and produced in accordance with said data-enable signal rises up, and a timing at which said vertical synchronization control signal rises up;

producing a HC-RC signal designed to be in a high level at a first timing at which said number of input horizontal synchronization control signals is equal to M wherein M indicates a predetermined positive integer;

producing a DC-RC signal designed to be in a high level at a second timing at which said number of input data-enable signals is equal to N wherein N indicates a predetermined positive integer smaller than said M;

producing a logical-sum signal designed to be in a high level at a timing at which at least one of said HC-RC signal and said DC-RC signal is in a high level;

resetting said HC-RC signal into a low level at an earlier timing among a timing at which said n-VALID signal falls down, and a timing at which said vertical synchronization control signal falls down;

resetting said DC-RC signal into a low level at an earlier timing among a timing at which said n-VALID signal falls down, and a timing at which said vertical synchronization control signal falls down; and

selecting said first mode if said number of input data-enable signals is equal to zero (0) at a timing at which said logical-sum signal was produced, and selecting said second mode if said number of input data-enable signals is not equal to zero (0) at said timing.