Thin film transistor array panel used for a liquid crystal display and a manufacturing method thereof
View Patent ↗An LCD includes an insulating substrate ( 30 ) with gate lines ( 32 ) and data lines ( 31 ) disposed thereon. The gate lines are parallel to each other and extend along a first direction, and the data lines are parallel to each other and extend along a second direction. The data lines cross the gate lines thereby defining a multiplicity of pixel regions ( 3 ). Each of the pixel regions includes a TFT ( 35 ), a pixel electrode ( 33 ) connected to the TFT, a common electrode ( 36 ) connected to a corresponding one of the data lines, and a dielectric layer ( 37 ) disposed between the common and pixel electrodes. The common electrode includes a plurality of protrusions ( 34 ). The protrusions, the dielectric layer, and the pixel electrode cooperatively define a storage capacitor ( 50 ) for holding the pixel region at a set voltage level until the next refresh cycle when the TFT is turned off.
1. A thin film transistor array panel used for a liquid crystal display, comprising:
a substrate;
a gate line formed on the substrate and extending in a first direction;
a gate electrode coupled to the gate line;
a gate insulating layer covering the gate line and the gate electrode;
a semiconductor layer on the gate insulating layer;
a doped semiconductor layer on the semiconductor layer;
a data line formed on the doped semiconductor layer, extending in a second direction and intersecting the gate line;
a source electrode coupled to the data line;
a drain electrode facing the source electrode with a gap therebetween on the semiconductor;
a passivation layer covering the data line and the source electrode and a part of the drain electrode; and
a pixel electrode coupled to the drain electrode,
wherein substantially the whole area of the data line is formed on the semiconductor layer and the doped semiconductor layer is formed only below the data line, the source electrode, and the drain electrode.
2. A thin film transistor array panel of claim 1 , wherein substantially the whole area of the data line has the same dimensions and pattern as the semiconductor layer which is between the gate insulating layer and the data line.
3. A thin film transistor array panel of claim 1 , wherein substantially the whole area of the source electrode is formed on the semiconductor layer.
4. A thin film transistor array panel of claim 3 , wherein substantially the whole area of the source electrode has the same dimensions and pattern as the semiconductor layer which is between the gate insulating layer and the source electrode.
5. A thin film transistor array panel used for a liquid crystal display, comprising:
a substrate;
a gate line formed on the substrate and extending in a first direction;
a gate electrode coupled to the gate line;
a gate insulating layer covering the gate line and the gate electrode;
a semiconductor layer on the gate insulating layer;
a doped semiconductor layer on the semiconductor layer;
a data line formed on the doped semiconductor layer, extending in a second direction and intersecting the gate line;
a source electrode coupled to the data line;
a drain electrode facing the source electrode with a gap therebetween on the semiconductor layer;
a passivation layer covering the data line and the source electrode and part of the drain electrode; and
a pixel electrode coupled to the drain electrode,
wherein substantially the whole area of the data line is formed on the doped semiconductor layer and the doped semiconductor layer is formed only below the data line, the source electrode, and the drain electrode.
6. A thin film transistor array panel of claim 5 , wherein substantially the whole area of the data line has the same dimensions and pattern as the doped semiconductor layer which is between the semiconductor layer and the data line.
7. A thin film transistor array panel of claim 5 , further comprising a conductive portion between the semiconductor layer and the passivation layer covering the gate line, and wherein a part of the conductive portion extends beyond the passivation layer and is connected to the pixel electrode.
8. A thin film transistor array panel of claim 5 , wherein substantially the whole area of the data line has the same dimensions and pattern as the semiconductor layer which is between the gate insulating layer and the data line.
9. A thin film transistor array panel of claim 5 , wherein substantially the whole area of the source electrode has the same dimensions and pattern as the semiconductor layer which is between the gate insulating layer and the source electrode.
10. A thin film transistor array panel used for a liquid crystal display, comprising:
a substrate;
a gate line formed on the substrate and extending in a first direction;
a gate electrode coupled to the gate line;
a gate insulating layer covering the gate line and the gate electrode;
a semiconductor layer on the gate insulating layer;
a doped semiconductor layer on the semiconductor layer;
a data line formed on the doped semiconductor layer, extending in a second direction and crossing over the gate line;
a source electrode electrically coupled to the data line;
a drain electrode facing the source electrode with a gap therebetween;
a passivation layer covering the data line and the source electrode and a part of the drain electrode; and
a pixel electrode electrically coupled to the drain electrode,
wherein substantially the whole area of the data line is formed on the semiconductor layer and the doped semiconductor layer is formed only below the data line, the source electrode, and the drain electrode.
11. A thin film transistor array panel of claim 10 , wherein substantially the whole area of the data line has the same dimensions and pattern as the semiconductor layer which is between the gate insulating layer and the data line.
12. A thin film transistor array panel of claim 10 , wherein substantially the whole area of the source electrode is formed on the semiconductor layer.
13. A thin film transistor array panel of claim 12 , wherein substantially the whole area of the source electrode has the same dimensions and pattern as the semiconductor layer which is between the gate insulating layer and the source electrode.
14. A thin film transistor array panel of claim 10 , further comprising a conductive portion between the semiconductor layer and the passivation layer overlapping a portion of the gate line, and wherein a part of the conductive portion extends beyond the passivation layer and is connected to the pixel electrode.