Data drive circuit for current writing type AMOEL display panel
View Patent ↗Data drive circuit for a current writing type AMOEL display panel including a plurality of current output channels, and a plurality of channel current generating circuits on respective current output channels for minimizing a difference of current levels occurred between the current output channels, each inclusive of one pair of transistors, a current generating part for generating a current of a small deviation proportional to square of a difference of threshold voltages of the one pair of the transistors, and a current mirror part for mirroring the current, and forwarding the mirrored current as a channel current for the channel, thereby minimizing a difference of current levels occurred between output channels, and driving the AMOEL display panel uniformly.
1. A data drive circuit for an AMOEL display panel comprising:
a pair of first transistors having a common gate terminal;
a second transistor for receiving an output current from the pair of first transistors;
a plurality of third transistors connected to a gate terminal of the second transistor, wherein the third transistor is formed a current mirror with the second transistor for mirroring the output current from the pair of first transistors; and,
a plurality of fourth transistors respectively connected to the plurality of third transistors in series, wherein outputs of the plurality of fourth transistors are connected in parallel.
2. A data drive circuit as claimed in claim 1 , further comprising a bias circuit connected to the common gate terminal of the pair of first transistors for prevention of floating of the common gate terminal.
3. A data drive circuit as claimed in claim 2 , wherein the bias circuit comprising at least one transistor connected between the common gate terminal of the pair of first transistor and a ground in series.
4. A data drive circuit as claimed in claim 3 , wherein the transistor is a NMOS transistor and a gate terminal of the transistor is connected to a second external bias voltage source.
5. A data drive circuit as claimed in claim 1 , wherein the first and the fourth transistors are PMOS transistors, and the second and the third transistors are NMOS transistors.
6. A data drive circuit as claimed in claim 1 , wherein one pair of first transistors has a body source connected together, which is connected to a first external bias voltage source, and the other of the pair of second transistors has a body and source connected together, which is connected to a positive voltage source.
7. A data drive circuit as claimed in claim 1 , wherein a pair of first transistors has the same widths and lengths.
8. A data drive circuit as claimed in claim 1 , wherein the fourth transistors control currents outputted from the third transistors in response to external n bit digital signals received as respective gate signal.
9. A data drive circuit as claimed in claim 1 , wherein currents outputted from the fourth transistors are added together in parallel and provided as one driving current to one of the current output channels.
10. A data drive circuit as claimed in claim 9 , wherein the driving current is regulated to have a current level of a binary form by combination of n bit digital signals received as gate signals of the fourth transistors.
11. A data drive circuit as claimed in claim 1 , wherein widths and lengths of the third transistors is fixed so that currents thereto are 2a (a=0, 1, 2, - - - ) times of the output current from the pair of first transistors.