Thin film transistor array panel and method for manufacturing the same

1. A thin film transistor (TFT) array panel, comprising:

an insulating substrate;

a gate line formed on the insulating substrate, the gate line having a first layer that includes Al, a second layer that includes Cu containing metal and is thicker than the first layer, and a gate electrode;

a gate insulating layer arranged on the gate line;

a semiconductor arranged on the gate insulating layer;

a data line having a source electrode, the data line being arranged on the gate insulating layer and the semiconductor;

a drain electrode arranged on the gate insulating layer and the semiconductor and facing the source electrode;

a passivation layer having a contact hole, the passivation layer arranged on the data line and the drain electrode; and

a pixel electrode arranged on the passivation layer and coupled with the drain electrode.

2. The TFT array panel of claim 1 , wherein the second layer is at least four times thicker than the first layer.

3. The TFT array panel of claim 1 , wherein the first layer is at least 5 Å thick.

4. The TFT array panel of claim 3 , wherein the first layer is about 5 Å to about 500 Å thick.

5. The TFT array panel of claim 1 , wherein the first layer includes Al—Nd.

6. The TFT array panel of claim 1 , wherein the data line includes at least one metal selected from among Cr, Mo, Al, Cu, and W.

7. The TFT array panel of claim 1 , wherein the pixel electrode includes ITO or IZO.

8. The TFT array panel of claim 1 , further comprising:

a color filter arranged on the insulating substrate and positioned below the pixel electrode.

9. An organic light emitting display (OLED), comprising:

a first semiconductor member and a second semiconductor member including a first intrinsic portion and a second intrinsic portion, respectively, and formed of an amorphous silicon or a polysilicon material;

a gate conductor having a first layer that includes Al, a second layer that includes Cu and is thicker than the first layer, and a gate line having a first gate electrode that overlaps the first intrinsic portion and a second gate electrode that overlaps the second intrinsic portion;

a gate insulating layer arranged between the first semiconductor member, the second semiconductor member, and the gate conductor;

a data conductor that includes a data line having a first source electrode coupled with the first semiconductor member, a first drain electrode opposing the first source electrode with respect to the first intrinsic portion and coupled with the first semiconductor member, a voltage transmission line that includes a second source electrode coupled with the second semiconductor member, and a second drain electrode opposing the second source electrode with respect to the second intrinsic portion and coupled with the second semiconductor member;

a pixel electrode coupled with the second drain electrode;

a partition having an opening exposing the pixel electrode;

an auxiliary electrode arranged on the partition and having substantially the same planar shape as the partition;

an organic light emitting member arranged on the pixel electrode and positioned substantially in the opening; and

a common electrode arranged on the light emitting member and the auxiliary electrode.

10. A thin film transistor (TFT) array panel for an LCD device, comprising:

a lower layer formed of a material containing aluminum (Al); and

an upper layer formed of a material containing copper (Cu),

wherein the upper layer and the lower layer are patterned to form a plurality of gate lines and the upper layer is thicker than the lower layer.

11. The TFT array panel of claim 10 , wherein the upper layer is at least four times thicker than the lower layer.

12. A liquid crystal display (LCD) comprising:

the TFT array panel of claim 1 ;

a color filter panel facing the TFT array panel and having a common electrode; and a liquid crystal layer arranged between the TFT array panel and the color filter panel.