Controller for controlling a source current to a memory cell, processing system and methods for use therewith
View Patent ↗A controller for controlling a source current of a memory cell for use in a static random access memory (SRAM) includes a bias generator for supplying a bias current to the memory cell. A read current generator controls the source current to the memory cell to a read current state when a column containing the memory cell is selected.
1. A controller for controlling a source current of a memory cell for use in a static random access memory (SRAM), the controller comprising:
a bias generator, operably coupled to the memory cell and a source voltage, for supplying a bias current to the memory cell; and
a read current generator, operably coupled to the memory cell and the source voltage, for controlling the source current to the memory cell to a read current state when a column containing the memory cell is selected by connecting the memory cell to one of: a boosted negative voltage and the source voltage, through a low impedance path.
2. The controller of claim 1 wherein the bias current is less than a normal read current.
3. The controller of claim 1 wherein the memory cell stores a binary value and wherein the bias current is sufficient to retain the binary value.
4. The controller of claim 1 wherein the read current generator includes a first transistor coupled to a column enable signal.
5. The controller of claim 4 wherein the first transistor is an n-channel metal oxide semiconductor (NMOS) transistor.
6. The controller of claim 4 wherein the first transistor turns on in response to the column enable signal.
7. The controller of claim 1 wherein the source current in the read current state is greater than the bias current.
8. The controller of claim 1 wherein the bias generator includes a second transistor.
9. The controller of claim 8 wherein the second transistor is an n-channel metal oxide semiconductor (NMOS) transistor.
10. A processing system comprising:
a processor,
static random access memory (SRAM) device, operably coupled to the processor, the SRAM device including:
a plurality of memory cells;
a column decoder for generating a column enable signal in response to an address input, the address input containing an address of a selected memory cell of the plurality of memory cells;
a row decoder, operably coupled to the plurality of memory cells and the address input, for activating a selected row of the plurality of memory cells that contains the selected memory cell;
a column multiplexer, operably coupled to the plurality of memory cells and the column decoder, for activating a selected column of the plurality of memory cells that contains the selected memory cell;
a data input, operably coupled to the column multiplexer, for writing data to the selected memory cell when a write command is received;
a sense amplifier, coupled to the column multiplexer for reading data from the selected memory cell when a read command is received;
a bias generator, operably coupled to the selected memory cell and a source voltage, for supplying a bias current to the selected memory cell; and
a read current generator, operably coupled to the selected memory cell and the source voltage, for controlling the source current to a read current state when the selected column of the plurality of memory cells containing the selected memory cell is activated by connecting the selected memory cell to one of: a boosted negative voltage and the source voltage, through a low impedance path.
11. The processing system of claim 10 wherein the bias current is less than a normal read current, wherein the selected memory cell stores a binary value and wherein the bias current is sufficient to retain the binary value.
12. The processing system of claim 10 wherein the read current generator includes a first transistor coupled to the column enable signal.
13. The processing system of claim 12 wherein the first transistor is an n-channel metal oxide semiconductor (NMOS) transistor.
14. The processing system of claim 12 wherein the first transistor turns on in response to the column enable signal.
15. The processing system of claim 10 wherein the source current in the read current state is greater than the bias current.
16. The processing system of claim 10 wherein the bias generator includes a second transistor.
17. The processing system of claim 16 wherein the second transistor is an n-channel metal oxide semiconductor (NMOS) transistor.
18. A method for use in controlling a source current of a memory cell of a static random access memory (SRAM), the method comprising:
controlling the source current to a read current state when a column containing the memory cell is selected by connecting the memory cell to one of: a boosted negative voltage and a source voltage, through a low impedance path; and
controlling the source current to a bias current state when the column containing the memory cell is not selected.
19. The method of claim 18 wherein the step of controlling the source current to the memory cell to a read current state includes turning on a first transistor in response to a column enable signal, the first transistor coupled to the memory cell and a source voltage.
20. The method of claim 18 wherein the source current in the read current state is greater than the source current in the bias current state.
21. The method of claim 18 wherein the bias current is less than a normal read current.
22. The method of claim 18 wherein the memory cell stores a binary value and wherein the bias current is sufficient to retain the binary value.