Integrated circuit devices with high and low voltage components and processes for manufacturing these devices
View Patent ↗The present invention includes a technique for making a dual voltage integrated circuit device. A gate dielectric layer is formed on a semiconductor substrate and a gate material layer is formed on the dielectric layer. A first region of the gate material layer is doped to a first nonzero level and a second region of the gate material level is doped to a second nonzero level greater than the first level. A first field effect transistor is defined that has a first gate formed from the first region. Also, a second field effect transistor is defined that has a second gate formed from the second region. The first transistor is operable at a gate threshold voltage greater than the second transistor in accordance with a difference between the first level and the second level.
1. A method of making an integrated circuit device, comprising:
forming a gate dielectric layer having a general uniform thickness of less than about 60 angstroms on a semiconductor substrate;
establishing a gate material layer on the dielectric layer;
implanting a first dopant into a first region of the gate material layer to a first nonzero level;
implanting a second dopant into a second region of the gate material to a second nonzero level greater than the first level;
thereafter covering said device to prevent alteration of the first and second nonzero levels; and
defining a first field effect transistor having a first gate formed from the first region and a second field effect transistor having a second gate formed from the second region, the first transistor being operable at a gate threshold voltage greater than the second transistor.
2. The method of claim 1 , wherein the first region and the second region are doped with at least one dopant of the same conductivity type.
3. The method of claim 2 , further comprising covering the device with a dopant blocking layer after said implanting a first dopant and before said implanting a second dopant to prevent alteration of the first level.
4. The method of claim 2 , wherein said implanting a second dopant implants the second dopant into the first region.
5. The method of claim 1 , wherein the first region is doped with a dopant of a first conductivity type and the second region is doped with a dopant of a conductivity type different from the first type.
6. The method of claim 5 , further comprising covering the device with a dopant blocking layer after said implanting a first dopant and before said implanting a second dopant to prevent alteration of the first level.
7. The method of claim 1 , wherein the first transistor is operable at a gate threshold voltage greater than the second transistor in accordance with a difference between the first level and the second level.
8. The method of claim 1 , wherein said defining includes patterning the gate dielectric layer and the gate material layer to define a source and drain for each of the first and second transistors.
9. The method of claim 1 , further comprising implanting the first dopant prior to implanting the second dopant.
10. The method of claim 1 , further comprising implanting the second dopant prior to implanting the first dopant.
11. A method of making an integrated circuit device, comprising:
forming a gate dielectric layer on a semiconductor substrate;
establishing a gate material layer on the dielectric layer;
doping the gate material layer, a first region of the gate material layer being doped to a first nonzero level and a second region of the gate material layer being doped to a second nonzero level greater than the first level;
covering the first and second regions with a dopant blocking layer after said doping to prevent alteration of the first and second levels; and
defining a first field effect transistor having a first gate formed from the first region and a second field effect transistor having a second gate formed from the second region after said covering, the first transistor being operable at a gate threshold voltage greater than the second transistor in accordance with a difference between the first level and the second level.
12. The method of claim 11 , wherein said defining includes patterning the gate dielectric layer and the gate material layer after said doping to provide the first and second gates and implanting a dopant in the substrate to define a source and drain for each of the first and second transistors.
13. The method of claim 11 , wherein said doping comprises doping the first region of the gate material layer with a dopant of a first conductivity type to a first nonzero level and doping the second region of the gate material layer with a dopant of the first conductivity type to a second nonzero level.
14. The method of claim 8 , wherein said implantings comprise doping the first region of the gate material layer with a dopant of a first conductivity type to a first nonzero level and doping the second region of the gate material layer with a dopant of the first conductivity type to a second nonzero level.
15. A method of making an integrated circuit device, comprising:
establishing a gate material layer on a dielectric layer;
doping the gate material layer, a first region of the gate material layer being doped to a first nonzero level and a second region of the gate material layer being doped to a second nonzero level greater than the first level;
protecting the first and second regions to prevent alteration of the difference between the first and second nonzero levels after said doping; and
defining a first field effect transistor having a first gate formed from the first region and a second field effect transistor having a second gate formed from the second region after said protecting, the first transistor being operable at a gate threshold voltage greater than the second transistor by a value determined by a difference between the first level and the second level.