IP Library Granted Patent US 7,960,767
Granted Patent B2
US 7,960,767 · App. 11/250,323 · Granted Jun 14, 2011

System for programmable gate array with sensor array

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,960,767
App. No.
11/250,323
Granted
Jun 14, 2011
Kind
B2
Abstract

The present invention provides providing a substrate, forming a sensor array on the substrate, forming a structured array of uncommitted logic surrounding the sensor array on the substrate, and providing electrical interconnects to the structured array of uncommitted logic, wherein the structured array of uncommitted logic forms functions that support the operation of the sensor array.

Claims (34)

1. A method of forming a semiconductor device comprising the steps of:

providing a substrate;

forming a sensor array on the substrate, the sensor array including a column/row address decoder, a pixel array, a correlated double sampler and an analog to digital converter; and

forming a structured array of uncommitted logic surrounding the sensor array on the substrate;

wherein the structured array of uncommitted logic is configurable to define functions that support the operation of the sensor array.

2. The method in claim 1 wherein forming the sensor array on the substrate further comprises forming an active pixel sensor.

3. The method in claim 1 wherein forming the structured array of uncommitted logic, on the substrate, surrounding the sensor array further comprises forming a gate array.

4. The method in claim 1 including providing electrical interconnects to the structured array of uncommitted logic by applying metal layers and vias.

5. The method in claim 1 further comprising providing I/O pads, on the substrate, surrounding the sensor array and the structured array of uncommitted logic.

6. A method for forming a semiconductor device comprising the steps of:

providing a substrate;

forming a sensor array, further comprising forming an active pixel sensor on the substrate, the sensor array including a column/row address decoder, a pixel array, a correlated double sampler and an analog to digital converter; and

forming a structured array of uncommitted logic surrounding the sensor array on the substrate;

wherein the structured array of uncommitted logic is configurable to define functions that support the operation of the sensor array.

7. The method in claim 6 wherein forming the structured array of uncommitted logic, on the substrate, surrounding the sensor array further comprises forming a gate array.

8. The method in claim 6 further comprising forming I/O pads, on the substrate, surrounding the sensor array and the structured array of uncommitted logic.

9. The method in claim 6 wherein forming the active pixel sensor further comprises forming a pixel array.

10. The method in claim 6 wherein forming the sensor array as an optical sensor forms an optical system on a chip.

11. A semiconductor system comprising:

a substrate;

a sensor array on the substrate, the sensor array including a column/row address decoder, a pixel array, a correlated double sampler and an analog to digital converter; and

a structured array of uncommitted logic surrounding the sensor array on the substrate;

wherein the structured array of uncommitted logic is configurable to define functions that support the operation of the sensor array.

12. The system in claim 11 wherein the sensor array on the substrate further comprises a pixel array.

13. The system in claim 11 wherein a structured array of uncommitted logic, on the substrate, surrounding the sensor array further comprises a gate array.

14. The system in claim 11 further comprising:

base logic circuits; and

electrical interconnects on the structured array of uncommitted logic that comprise metal layers and vias connecting the base logic circuits to form the functions that support the operation of the sensor arrays.

15. The system in claim 11 further comprising I/O pads, on the substrate, surrounding the sensor array and the structured array of uncommitted logic.

16. The system in claim 11 wherein the sensor array further comprises a sequence and timing block, and a signal multiplexer.

17. The system in claim 11 further comprises having a phase locked loop (PLL) for synchronizing the movement of pixel data within a chip.

18. The system in claim 11 wherein the structured array of uncommitted logic further comprises a micro-controller system configuration for managing movement of pixel data.

19. The system in claim 11 wherein the sensor array, on the substrate further comprises a scalable array size by the use of at least one of metal layers and vias or e-beam trimming.

20. The system in claim 11 further wherein the sensor array is an optical sensor for configuring an optical system on a chip.

Assignments (1)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 017206 FRAME: 0666. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2016
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038632/0662 →