IP Library Granted Patent US 7,504,813
Granted Patent B2
US 7,504,813 · App. 11/250,375 · Granted Mar 17, 2009

High precision power detector

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Quick Facts
Patent No.
US 7,504,813
App. No.
11/250,375
Granted
Mar 17, 2009
Kind
B2
Abstract

A power detector having temperature compensation for improved measurement performance includes a pair of rectifier transistors coupled to a differential input signal biased by a first temperature dependent current. An output of the pair of rectifier transistors provides a first component of a differential DC output signal. The first component of the differential DC output signal includes a DC voltage proportional to an amplitude of the differential input signal plus an offset voltage. The power detector further includes a reference transistor biased by a reference current. The reference current includes a second temperature dependent current and a temperature independent offset current for temperature compensation. An output of the reference transistor provides a second component of the differential DC output signal that includes a reference voltage. The temperature independent offset current is adjusted such that the reference voltage substantially equals the offset voltage, thereby improving the precision of the power detector.

Claims (36)

1. A power detector, comprising:

a pair of rectifier transistors coupled to a differential input signal and biased by a first temperature dependent current;

a capacitor coupled to an output of the pair of rectifier transistors to provide a first component of a differential DC output signal; and

a reference transistor biased by a reference current and having an output to provide a second component of the differential DC output signal;

wherein the reference current comprises a second temperature dependent current and a temperature independent offset current.

2. The power detector of claim 1 , wherein:

the first component of the differential DC output signal comprises a DC voltage proportional to an amplitude of the differential input signal plus an offset voltage; and

the second component of the differential DC output signal comprises a reference voltage.

3. The power detector of claim 2 , wherein the temperature independent offset current is adjusted such that the reference voltage is substantially equal to the offset voltage.

4. The power detector of claim 3 , wherein the temperature independent offset current is adjusted based on an expected range of the amplitude of the differential input signal.

5. The power detector of claim 3 , wherein the temperature independent offset current is set at a constant level based on a constant input power level of the differential input signal.

6. The power detector of claim 3 , further comprising a feedback circuit to adjust the temperature independent offset current.

7. The power detector of claim 6 , wherein the feedback circuit is coupled to the output of the pair of rectifier transistors and the output of the reference transistor.

8. The power detector of claim 7 , wherein the feedback circuit adjusts the temperature independent offset current based on a difference between the first component of the differential DC output signal and the second component of the differential DC output signal.

9. The power detector of claim 1 , wherein the second temperature dependent current is a fraction of the first temperature dependent current.

10. The power detector of claim 9 , wherein the second temperature dependent current is approximately one-half of the first temperature dependent current.

11. The power detector of claim 1 , wherein the temperature independent offset current is generated by an external current source.

12. The power detector of claim 1 , wherein each transistor comprises a Bipolar Junction Transistor (BJT).

13. The power detector of claim 1 , wherein each transistor comprises a Metal Oxide Semiconductor Field-Effect Transistor (MOSFET).

14. The power detector of claim 1 , wherein the differential input signal is a differential radio frequency (RF) signal.

15. A method for measuring the amplitude of a differential input signal, comprising:

(1) biasing a pair of rectifier transistors with a first temperature dependent current source;

(2) rectifying a differential input signal using the pair of rectifier transistors to provide a first component of a differential DC output signal; and

(3) biasing a reference transistor using a reference current to provide a second component of the differential DC output signal;

wherein the reference current comprises a second temperature dependent current and a temperature independent offset current.

16. The method of claim 15 , further comprising the step of:

(4) generating a difference signal proportional to an amplitude of the differential input signal by subtracting the second component of the differential DC output signal from the first component of the differential DC output signal.

17. The method of claim 16 , wherein step (3) further comprises

(a) adjusting the temperature independent offset current based on the difference signal such that the second component of the differential DC output signal is substantially equal to an offset of the first component of the differential DC output signal.

18. A power detector, comprising:

a pair of rectifier transistors coupled to a differential input signal and biased by a first temperature dependent current, wherein an output of the pair of rectifier transistors provides a first component of a differential DC output signal; and

a reference transistor biased by a reference current, wherein an output of the reference transistor provides a second component of the differential DC output signal;

wherein the reference current comprises a second temperature dependent current and a temperature independent offset current.

19. The power detector of claim 18 , wherein:

the first component of the differential DC output signal comprises a DC voltage proportional to an amplitude of the differential input signal plus an offset voltage; and

the second component of the differential DC output signal comprises a reference voltage substantially equal to the offset voltage.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED AT REEL: 047195 FRAME: 0827. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Nov 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047924/0571 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0827 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →