Complementary linear feedback shift registers for generating advance timing masks
A mask required to generate a time-offset version of a PN code may be generated by constructing a Galois linear feedback shift register (LFSR) that is complementary to a Fibonacci LFSR that generates the PN code, clocking the Galois LFSR a number of times equal to the time offset, and reading the state of the Galois LFSR, which is the desired mask.
1 . A method for generating a linear feedback shift register (LFSR) mask for a first LFSR, comprising:
providing for a second LFSR that is complementary to the first LFSR,
providing for clocking the second LFSR a number of times equal to a desired timing advance, and
providing for using a state of the second LFSR as the LFSR mask for the first LFSR.
2 . The method recited in claim 1 , wherein the first LFSR is a Galois LFSR and the second LFSR is a Fibonacci LFSR.
3 . The method recited in claim 1 , wherein the first LFSR is a Fibonacci LFSR and the second LFSR is a Galois LFSR.
4 . The method recited in claim 1 , wherein the mask is configured to generate in-phase and quadrature terms of a Gold code.
5 . A subscriber-side device configured to perform the method recited in claim 1 .
6 . A server-side device configured to perform the method recited in claim 1 .
7 . A searcher/tracker circuit configured to perform the method recited in claim 1 .
8 . A circuit configured to compute at least one mask for a first LFSR, comprising:
a second LFSR that is complementary to the first LFSR,
a shift-value input to the second LFSR, the shift-value input configured for clocking the second LFSR a number of times equal to a desired timing advance, and
a state input to the first LFSR configured for receiving a state of the second LFSR as the at least one mask for the first LFSR.
9 . The circuit recited in claim 8 , wherein the first LFSR is a Galois LFSR and the second LFSR is a Fibonacci LFSR.
10 . The circuit recited in claim 8 , wherein the first LFSR is a Fibonacci LFSR and the second LFSR is a Galois LFSR.
11 . The circuit recited in claim 8 , wherein the mask is configured to generate in-phase and quadrature terms of a Gold code.
12 . The circuit recited in claim 8 configured to operate in a subscriber-side device.
13 . The circuit recited in claim 8 configured to operate in a server-side device.
14 . The circuit recited in claim 8 configured to operate in a searcher/tracker circuit.
15 . A computer-readable memory configured to compute at least one mask for a first LFSR, said computer-readable memory configured for implementing the steps of:
providing for a second LFSR that is complementary to the first LFSR,
providing for clocking the second LFSR a number of times equal to a desired timing advance, and
providing for receiving a state of the second LFSR as the at least one mask for the first LFSR.
16 . The computer-readable memory recited in claim 15 , wherein the first LFSR is a Galois LFSR and the second LFSR is a Fibonacci LFSR.
17 . The computer-readable memory recited in claim 15 , wherein the first LFSR is a Fibonacci LFSR and the second LFSR is a Galois LFSR.
18 . The computer-readable memory recited in claim 15 , wherein the mask is configured to generate in-phase and quadrature terms of a Gold code.
19 . The computer-readable memory recited in claim 15 configured to reside on a subscriber-side device.
20 . The computer-readable memory recited in claim 15 configured to reside on a server- side device.
21 . The computer-readable memory recited in claim 15 configured to reside in a searcher/tracker circuit.