Driving system of liquid crystal display
A driving system of a liquid crystal display includes a pixel data line, a timing controller, a source driver and a gate driver. The pixel data line provides pixel data to the source driver directly. The timing controller is operative to receive a clock signal and a synchronization signal, so as to output a source control signal and a gate control signal. The source driver receives the clock signal, the source control signal and the pixel data, so as to output an image data signal. Upon receiving the gate control signal, the gate driver is operative to output an on/off signal.
1 . A driving circuit for a liquid crystal display, comprising:
a timing controller for receiving a clock signal and a synchronization signal and outputting a source control signal and a gate control signal;
a source driver electrically connected to the timing controller for receiving the source control signal;
a gate driver electrically connected to the timing controller for receiving the gate control signal, so as to output an on/off signal; and
a pixel data line directly connected to the source driver to provide a pixel data thereto,
wherein the source driver is operative to output an image data signal by receiving the clock signal, the source control signal and the pixel data directly.
2 . The driving system of claim 1 , wherein the timing controller is mounted on a control board.
3 . The driving system of claim 1 , wherein the source driver is carried by a tape carrier package or a glass substrate package.
4 . The driving system of claim 3 , wherein the source driver is connected to an X board.
5 . The driving system of claim 1 , wherein gate driver is carried by a tape carrier package or a glass substrate package.
6 . The driving system of claim 5 , wherein the gate driver is connected to a Y board.
7 . The driving system of claim 1 , wherein the timing controller is integrated with the source driver into an integrated source driver.
8 . The driving system of claim 7 , further comprising an indication signal line connected to the integrated source driver to indicate the status of the source driver.
9 . The driving system of claim 7 , wherein the integrated source driver is carried by a tape carrier package or a glass substrate package.
10 . The driving system of claim 1 , wherein the timing controller is integrated with the gate driver into an integrated gate driver.
11 . The driving system of claim 10 , wherein the integrated gate controller is carried by a tape carrier package or a glass substrate package.
12 . A driving system of a liquid crystal display, comprising:
a pixel data line to provide a pixel data;
an integrated source driver including:
a timing controller for receiving a clock signal and a synchronization signal and outputting a source control signal and a gate control signal; and
a source driver for receiving the clock signal, the source control signal and the pixel data so as to output an image data signal; and
a gate driver for receiving the gate control signal so as to output an on/off signal.
13 . The driving system of claim 12 , wherein the integrated source driver is carried by a tape carrier package or a glass substrate package.
14 . The driving system of claim 12 , further comprising an indication signal line connected to the integrated source driver to indicate the status of the source driver.
15 . A driving system of a liquid crystal display, comprising:
a pixel data line to provide a pixel data;
an integrated gate driver including:
a timing controller for receiving a clock signal and a synchronization signal and outputting a source control signal and a gate control signal; and
a gate driver for receiving the gate control signal so as to output an on/off signal; and
a source driver for receiving the clock signal, the source control signal and the pixel data so as to output an image data signal.
16 . The driving system of claim 15 , wherein the integrated gate driver is carried by a tape carrier package or a glass substrate package.
17 . The driving system of claim 15 , further comprising an indication signal line connected to the integrated gate driver to indicate the status of the gate driver.