Solderable top metal for SiC device
View Patent ↗A silicon carbide device includes at least one power electrode on a surface thereof, a solderable contract formed on the power electrode, and at least one passivation layer that surrounds the solderable contact but is spaced from the solderable contract, thereby forming a gap.
1. A semiconductor device comprising:
a silicon carbide substrate having a top surface;
at least one power electrode over said top surface of said substrate;
a passivation layer over said top surface of said substrate and disposed on an outer peripheral edge of said power electrode; and
a solderable contact disposed on a portion of a top surface of said power electrode, said solderable contact being a spaced distance from said passivation layer such that adjacent sides of said solderable contact and said passivation layer form a gap that extends to the top surface of said power electrode.
2. The semiconductor device of claim 1 , wherein top and side surfaces of said solderable contact are entirely exposed for solder connection.
3. The semiconductor device of claim 2 , wherein said solderable contact is a silver-containing contact and wherein after soldering, the entire top and side surfaces of said solderable contact are fully converted to a solder alloy.
4. The semiconductor device of claim 1 , wherein said gap is from about 5 um wide to about 80 um wide.
5. The semiconductor device of claim 1 , wherein said solderable contact includes silver.
6. The semiconductor device of claim 1 , wherein said solderable contact is a solderable trimetal, a top portion of said trimetal being composed of silver.
7. The semiconductor device of claim 1 , wherein said passivation layer is an amorphous silicon layer.
8. The semiconductor device of claim 1 , wherein said passivation layer is a first passivation layer and wherein said device further comprises a second passivation layer disposed over said first passivation layer.
9. The semiconductor device of claim 8 , wherein said second passivation layer extends up to said gap such that a side of said second passivation layer is adjacent to the side of said solderable contact, thereby further defining said gap.
10. The semiconductor device of claim 9 , wherein the side of said solderable contact extends to a first height above the top surface of said substrate and the side of said second passivation layer extends to a second height above the top surface of said substrate, and wherein said second height is about equal to or greater than said first height.
11. The semiconductor device of claim 8 , wherein said second passivation layer is either a photo imagable polyimide layer, a PSG oxide layer or a silicon nitride layer.
12. The semiconductor device of claim 1 , wherein said device is a Schottky diode and wherein said at least one power electrode is an anode electrode.
13. The semiconductor device of claim 12 , further comprising a termination region that includes at least one guard ring.
14. The semiconductor device of claim 13 , wherein said device is capable of supporting from about 300V up to about 1600V of blocking voltage.
15. The semiconductor device of claim 1 , further comprising a conductive clip or a leadframe electrically connected to said solderable contact.
16. A semiconductor device comprising:
a silicon carbide substrate having a top surface;
at least one power electrode over said top surface of said substrate;
a first passivation layer over said top surface of said substrate and surrounding an outer peripheral edge of said power electrode;
a second passivation layer over said first passivation layer and surrounding the outer peripheral edge of said power electrode; and
a solderable contact disposed on a portion of a top surface of said power electrode, said solderable contact being a spaced distance from said first and second passivation layers such that said solderable contact and said first and second passivation layers form a gap there between.
17. The semiconductor device of claim 16 , wherein said gap is from about 5 um wide to about 80 um wide.
18. The semiconductor device of claim 16 , wherein said first passivation layer is amorphous silicon layer and said second passivation layer is either a photo imagable polyimide layer, a PSG oxide layer, or a silicon nitride layer.
19. The semiconductor device of claim 16 , wherein adjacent sides of said solderable contact and said second passivation layer form a portion of said gap, and wherein side adjacent sides extend to approximately the same height above the top surface of said substrate.
20. The semiconductor device of claim 16 , wherein top and side surfaces of said solderable contact are entirely exposed for solder connection, wherein said solderable contact is a silver-containing contact, and wherein after soldering, the entire top and side surfaces of said solderable contact are fully converted to a solder alloy.