Processor cluster architecture and associated parallel processing methods
View Patent ↗A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors assigned to a particular task) over the code distribution bus, and are executed in parallel by these processors. A task control processor determines when all of the processors assigned to a particular task have finished executing the current code page, and then loads a new code page (e.g., the next sequential code page within a task) into the program memories of these processors for execution. The processors within the cluster preferably share a common memory (1 per cluster) that is used to receive data inputs from, and to provide data outputs to, a higher level processor. Multiple interconnected clusters may be integrated within a common integrated circuit device.
1. A method of executing a task in parallel on a plurality of processors, the method comprising:
(a) storing a sequence of code pages of said task in a common program memory;
(b) broadcasting a current code page of said sequence of code pages on a code distribution bus to concurrently load the current code page into a plurality of local memories of the plurality of processors;
(c) monitoring the plurality of processors to determine whether all of the processors have completed execution of the current code page from their corresponding local memories; and
(d) after all of the processors have finished executing the current code page, repeating (b) and (c) with a next sequential code page of said sequence treated as the current code page, at least until all code pages of the sequence have been executed;
whereby each code page of the sequence is executed in parallel by the plurality of processors.
2. The method of claim 1 , wherein the method comprises processing a different respective dataset with each of the plurality of processors.
3. The method of claim 1 , wherein the task is a voice processing task, and
the method comprises processing a plurality of voice data streams in parallel with the plurality of processors.
4. The method of claim 1 , wherein each processor executes the current code page from a different respective local memory.
5. The method of claim 1 , wherein each of the local memories is shared by two of the processors.
6. The method of claim 1 , wherein each code page of said sequence has a size of less than 4K instruction words.
7. The method of claim 1 , wherein broadcasts of code pages on the code distribution bus in step (b) are interleaved with broadcasts of code pages of a second task to a second plurality of processors.
8. The method of claim 1 , wherein the method is performed entirely within an integrated circuit.
9. The method of claim 1 , wherein steps (b)–(d) are performed by a task control processor that executes a control program.