Method of manufacturing array substrate for liquid crystal display device
View Patent ↗A method of manufacturing an array substrate for a liquid crystal display device which includes forming a gate electrode, a gate line, and a gate pad on a substrate by sequentially depositing a metal layer and a transparent conductive layer and patterning, forming a gate insulating layer on the gate electrode, the gate line, and the gate pad, forming an active layer on the gate insulating layer over the gate electrode, forming an ohmic contact layer on the active layer, forming source and drain electrodes, a data line and a data pad on the ohmic contact layer, forming a pixel electrode, forming a data pad terminal covering the data pad, forming a passivation layer on the pixel electrode and the data pad terminal, exposing the gate pad by etching the passivation layer and the gate insulating layer, and exposing the data pad terminal by etching the passivation layer.
1. A method of manufacturing an array substrate for a liquid crystal display device, said method comprising:
forming a gate electrode, a gate line, and a gate pad on a substrate by sequentially depositing a metal layer and a transparent conductive layer and patterning, the metal layer and the transparent electrode having edges which coincide with each other after forming the gate electrode, the gate line and the gate pad;
forming a gate insulating layer on the gate electrode, the gate line, and the gate pad;
forming an active layer on the gate insulating layer over the gate electrode;
forming an ohmic contact layer on the active layer;
forming source and drain electrodes, a data line and a data pad on the ohmic contact layer;
forming a pixel electrode contacting the drain electrode;
forming a data pad terminal covering the data pad;
forming a passivation layer on the pixel electrode and the data pad terminal;
exposing the gate pad by etching the passivation layer and the gate insulating layer; and
exposing the data pad terminal by etching the passivation layer.
2. The method according to claim 1 , wherein the transparent conductive layer is selected from the group consisting of indium-tin-oxide (ITO) and indium-zinc-oxide (IZO).
3. The method according to claim 1 , wherein the step of forming the active layer and the step of forming the source and drain electrodes, the data line and the data pad are processed through one photolithographic process.
4. The method according to claim 3 , wherein the photolithographic process uses a diffraction exposure technique.
5. The method according to claim 1 , wherein the gate insulating layer and the passivation layer contain silicon nitride or silicon oxide.
6. The method according to claim 5 , wherein the etchant for etching the passivation layer includes hydrogen fluoride (HF).
7. The method according to claim 1 , wherein the step of forming the data pad terminal is carried out simultaneously with the step of forming the pixel electrode.