Memory, processing system and methods for use therewith
View Patent ↗A memory includes a selected bitline coupled to the array of memory cells. A column multiplexer passes a signal on the selected bitline to a sense amplifier input in response to a column enable signal. A multiplexer output conditioner discharges the sense amplifier input and a bitline conditioner precharges and readjusts the selected bitline to a precharge threshold. A sense amplifier produces a data output that is based on the sense amplifier input.
1. A memory comprising:
an array of memory cells;
a selected bitline operably coupled to the array of memory cells;
a column multiplexer, operably coupled to the selected bitline, for passing a signal on the selected bitline as sense amplifier input in response to a column enable signal;
a multiplexer output conditioner for discharging the sense amplifier input;
a bitline conditioner, operably coupled to the selected bitline, for precharging the selected bitline prior to the discharging of the sense amplifier input and readjusting the selected bitline to a precharge threshold after the sense amplifier input is discharged; and
a sense amplifier, operably coupled to the sense amplifier input, for producing a data output.
2. The memory of claim 1 wherein the bitline conditioner includes an n-channel metal oxide semiconductor (NMOS) transistor.
3. The memory of claim 1 wherein the column multiplexer includes an n-channel metal oxide semiconductor (NMOS) transistor.
4. The memory of claim 1 wherein the multiplexer output conditioner includes an n-channel metal oxide semiconductor (NMOS) transistor having a drain coupled to the sense amplifier input, a source coupled to a source voltage and a gate coupled to a discharge control signal.
5. The memory of claim 4 wherein the discharge control signal includes a pulse of predetermined duration.
6. The memory of claim 4 wherein the discharge control signal includes a pulse having a length determined by a voltage level detector.
7. The memory of claim 4 wherein the multiplexer output conditioner further includes a p-channel metal oxide semiconductor (PMOS) transistor having a source coupled to the sense amplifier input, a drain coupled to a drain voltage and a gate coupled to a sense amplifier precharge signal.
8. The memory of claim 1 wherein the multiplexer output conditioner discharges the sense amplifier input and the bitline conditioner precharges and readjusts the selected bitline prior to the activation of a wordline during a read operation.
9. A processing system comprising:
a processor,
memory device, operably coupled to the processor, the memory device including:
an array of memory cells;
a selected bitline operably coupled to the array of memory cells;
a column multiplexer, having an input node operably coupled to the selected bitline and an output node operably coupled to a sense amplifier input, for passing a signal on the selected bitline as the sense amplifier input in response to a column enable signal;
a multiplexer output conditioner for discharging the sense amplifier input;
a bitline conditioner, operably coupled to the input node of the column multiplexer, for precharging and readjusting the selected bitline to a precharge threshold; and
a sense amplifier, operably coupled to the sense amplifier input for producing a read data bit.
10. The processing system of claim 9 wherein the bitline conditioner includes an n-channel metal oxide semiconductor (NMOS) transistor.
11. The processing system of claim 9 wherein the column multiplexer includes an n-channel metal oxide semiconductor (NMOS) transistor.
12. The processing system of claim 9 wherein the multiplexer output conditioner includes an n-channel metal oxide semiconductor (NMOS) transistor having a drain coupled to the sense amplifier input, a source coupled to a source voltage and a gate coupled to a discharge control signal.
13. The processing system of claim 12 wherein the discharge control signal includes a pulse of predetermined duration.
14. The memory of claim 12 wherein the discharge control signal includes a pulse having a length determined by a voltage level detector.
15. The processing system of claim 11 wherein the multiplexer output conditioner further includes a p-channel metal oxide semiconductor (PMOS) transistor having a source coupled to the sense amplifier input, a drain coupled to a drain voltage and a gate coupled to a sense amplifier precharge signal.
16. The processing system of claim 9 wherein the multiplexer output conditioned discharges the sense amplifier input and the bitline conditioner precharges and readjusts the selected bitline prior to the activation of a wordline during a read operation.
17. A method of conditioning a sense amplifier input of a memory array during a read operation, the method comprising the steps of:
precharging a selected billing to a bitline precharge level;
discharging the sense amplifier input; and
readjusting the selected bitline to a precharge threshold.
18. The method of claim 17 wherein the step of discharging includes discharging a multiplexer output for a predetermined duration.
19. The method of claim 17 wherein the step of discharging the sense amplifier input is performed prior to activation of a wordline during the read operation.
20. The method of claim 17 wherein the step of precharging and readjusting the selected bitline is performed prior to activation of a wordline during the read operation.
21. A memory comprising:
an array of memory cells;
a selected bitline operably coupled to the array of memory cells;
a column multiplexer, operably coupled to the selected bitline, for passing a signal on the selected bitline as sense amplifier input in response to a column enable signal;
a multiplexer output conditioner for discharging the sense amplifier input, wherein the multiplexer output conditioner includes an n-channel metal oxide semiconductor (NMOS) transistor having a drain coupled to the sense amplifier input, a source coupled to a source voltage and a gate coupled to a discharge control signal, and wherein the discharge control signal includes a pulse having a length determined by a voltage level detector;
a bitline conditioner, operably coupled to the input node of the column multiplexer, for precharging and readjusting the selected bitline to a precharge threshold; and
a sense amplifier, operably coupled to the sense amplifier input, for producing a data output.
22. The memory of claim 21 wherein the bitline conditioner includes an n-channel metal oxide semiconductor (NMOS) transistor and wherein the column multiplexer includes an n-channel metal oxide semiconductor (NMOS) transistor.
23. The memory of claim 21 wherein the multiplexer output conditioner further includes a p-channel metal oxide semiconductor (PMOS) transistor having a source coupled to the sense amplifier input, a drain coupled to a drain voltage and a gate coupled to a sense amplifier precharge signal.