Setting of the impedance ratio of a balun
The modification of the impedance ratio of a balun of four conductive windings formed in two metallization planes stacked by being interdigited and electrically in series two by two, by connecting a capacitor in series with the two windings defining the common mode of the balun.
1. A balun of distributed type, formed of planar conductive windings defining inductive elements comprising:
in a first conductive level, a first winding between a first common-mode access and a first central end and a second winding between a first differential-mode access and a second central end;
in a second conductive level, a third winding having a central end electrically connected to the first central end of the first level and having an external end defining a second common-mode access, and a fourth winding having an external end defining a second differential-mode access and having a central end electrically connected to the second central end of the first level; and
a third conductive level forming a ground plane to which are electrically connected the central interconnected ends of the second and fourth differential-mode windings,
the external end of the third winding being electrically connected to a surface defining a first electrode of a capacitor having a second electrode connected to the ground plane, and the value of the capacitor being selected according to the impedance ratio desired for the transformer.
2. The transformer of claim 1 , wherein all the conductive windings have same dimensions, selected according to the central operating frequency desired for the transformer.
3. The transformer of claim 1 , wherein the second electrode of the capacitor is formed directly by the ground plane.
4. A distributed balun, comprising:
a first winding formed in a first level;
a second winding formed in the first level and interdigitated with the first winding;
a third winding formed in a second level;
a fourth winding formed in the second level and interdigitated with the third winding; and
a capacitor coupled to the third winding and having a value selected to establish a desired impedance ratio for the balun;
wherein the value of the capacitor is selected such that the distributed balun has a non-unity impedance ratio.
5. The distributed balun of claim 4 , wherein the first, second, third and fourth windings are aligned with one another so as to form a single stack.
6. A distributed balun, comprising:
a first winding formed in a first level;
a second winding formed in the first level and interdigitated with the first winding;
a third winding formed in a second level;
a fourth winding formed in the second level and interdigitated with the third winding, wherein the second winding is connected in series with the fourth winding;
a capacitor coupled to the third winding and having a value selected to establish a desired impedance ratio for the balun; and
a ground plane connected to the second and fourth windings at a node connecting the second and fourth windings, the ground plane being formed in a third level different from the first and second levels.
7. The distributed balun of claim 6 , wherein a first electrode of the capacitor is formed in the second level and the ground plane provides a second electrode of the capacitor.
8. The distributed balun of claim 6 , wherein the second and fourth windings are connected by a via that extends between a central portion of the second winding and a central portion of the fourth winding.
9. The distributed balun of claim 6 , wherein the first and third windings are connected in series by a via that extends between a central portion of the first winding and a central portion of the third winding.
10. The distributed balun of claim 6 , further comprising an insulator that separates the first level from the second level, wherein a thickness of the insulator separating the first and second levels has no substantial effect on a coupling between common and differential modes of the distributed balun.
11. The distributed balun of claim 6 , wherein the distributed balun is of Marchand-type.
12. The distributed balun of claim 6 , wherein the value of the capacitor is selected such tat the distributed balun has a non-unity impedance ratio.
13. The distributed balun of claim 6 , wherein the distributed balun is configured such that the value of the capacitor has no substantial effect on a central frequency of operation of the distributed balun.
14. The distributed balun of claim 6 , wherein the first, second, third and fourth windings are aligned with one another so as to form a single stack.
15. The distributed balun of claim 14 , wherein the first winding comprises a first common-mode access terminal, the second winding comprises a first differential-mode access terminal, the third winding comprises a second common-mode access terminal and the fourth winding comprises a second differential-mode access terminal.
16. A distributed balun, comprising:
a first winding formed in a first level;
a second winding formed in the first level and interdigitated with the first winding;
a third winding formed in a second level;
a fourth winding formed in the second level and interdigitated with the third winding; and
a capacitor having a value selected to establish a desired impedance ratio for the balun, the capacitor being coupled to the third winding;
wherein the first, second, third and fourth windings are arranged in a single stack.
17. The distributed balun of claim 16 , wherein the first winding comprises a first common-mode access terminal, the second winding comprises a first differential-mode access terminal, the third winding comprises a second common-mode access terminal and the fourth winding comprises a second differential-mode access terminal.
18. The distributed balun of claim 16 , wherein the first winding is connected in series with the third winding and the second winding is connected in series with the fourth winding.
19. The distributed balun of claim 16 , wherein first level comprises a first metallization level of an integrated circuit and the second level comprises a second metallization level of the integrated circuit.