Method for booting a system on a chip integrated circuit
View Patent ↗A method for booting a system on a chip (IC) integrated circuit includes reading a warm boot flag stored in a persistent register of an analog portion of the system on a chip IC. A warm boot procedure is executed when the warm boot flag is set.
1. A method for restarting a system on a chip integrated circuit (IC), the method comprising:
running a hibernate sequence, in response to a hibernate signal, to place the system on a chip IC in a hibernate mode;
receiving a power up command;
reading a warm boot flag stored in a persistent register of an analog portion of the system on the chip IC, the analog portion including a power-off timer; and
executing a warm boot procedure when the warm boot flag is set, wherein the warm boot procedure includes reading a memory index from the persistent register and programming a memory controller with the memory index, wherein the memory index is an index to a table for memory parameters that correspond to an external memory device.
2. The method for restarting the system on a chip IC of claim 1 further comprising:
executing a cold boot procedure when the warm boot flag is not set.
3. The method for restarting the system on a chip IC of claim 1 wherein the table for memory parameters that correspond to the external memory device is a read-only memory (ROM) table.
4. The method for restarting the system on a chip IC of claim 1 wherein the warm boot procedure further includes retrieving from a read only memory device at least one of: a memory timing parameter, and a memory size parameter.
5. The method for restarting the system on a chip IC of claim 1 wherein the warm boot procedure further includes changing the external memory device from a low power state to an active state.
6. The method for restarting the system on a chip IC of claim 1 wherein the warm boot procedure further includes loading a jump address stored in a jump vector and jumping to a warm boot code section stored in the external memory device beginning at the jump address.
7. The method for restarting the system on a chip IC of claim 6 wherein the warm boot procedure further includes copying a portion of the external memory device to an on-chip memory.
8. The method for restarting the system on a chip IC of claim 1 wherein the warm boot procedure further includes disabling the power-off timer.
9. The method for restarting the system on a chip IC of claim 1 wherein running the hibernate sequence includes setting the warm boot flag in the persistent register.
10. The method for restarting the system on a chip IC of claim 1 wherein running the hibernate sequence includes writing at least one memory parameter to the persistent register.
11. The method for restarting the system on a chip IC of claim 1 wherein running the hibernate sequence includes copying a portion of an on-chip memory to the external memory device.
12. The method for restarting the system on a chip IC of claim 11 wherein running the hibernate sequence includes storing a jump address in a jump vector of the external memory device.
13. The method for restarting the system on a chip IC of claim 12 wherein running the hibernate sequence includes changing the external memory device from an active state to a low power state.
14. The method for restarting the system on a chip IC of claim 1 wherein running the hibernate sequence includes setting the power-off timer for the analog portion of the system on a chip IC.
15. The method for restarting the system on a chip IC of claim 1 wherein running the hibernate sequence includes powering off the analog portion of the system on a chip IC when the power-off timer expires before receiving the power-up command.
16. The method for restarting the system on a chip IC of claim 1 wherein the system on a chip IC further includes a digital portion and wherein running the hibernate sequence includes powering off the digital portion.
17. A system on a chip integrated circuit (IC) comprising:
an analog portion that includes a persistent register and a power-off timer;
a digital portion, operably coupled to the analog portion, the digital portion including a processor that, during a boot procedure, executes operational instructions that include:
reading a warm boot flag stored in the persistent register; and
executing a warm boot procedure when the warm boot flag is set, wherein the warm boot procedure includes reading a memory index from the persistent register and programming a memory controller with the memory index, wherein the memory index is an index to a table for memory parameters that correspond to an external memory device, wherein the analog portion can remain in an on-state, while the digital portion is in an off-state.
18. The system on a chip IC of claim 17 wherein the table for memory parameters that correspond to the external memory device is a read-only memory (ROM) table.
19. The system on a chip IC of claim 17 wherein the operational instructions further include:
executing a cold boot procedure when the warm boot flag is not set.
20. The system on a chip IC of claim 17 wherein the memory controller is operably coupled to the external memory device.
21. The system on a chip IC of claim 17 wherein the digital portion further includes a read only memory device, and wherein the warm boot procedure further includes retrieving from the read only memory device at least one of: a memory timing parameter, and a memory size parameter.
22. The system on a chip IC of claim 20 wherein the warm boot procedure further includes changing the external memory device from a low power state to an active state.
23. The system on a chip IC of claim 20 wherein the warm boot procedure further includes loading a jump address stored in the external memory device and jumping to a warm boot code section stored in the external memory device beginning at the jump address.
24. The system on a chip IC of claim 23 wherein the digital portion further includes an on-chip memory and wherein the warm boot procedure further includes copying a portion of the external memory device to an on-chip memory.
25. The system on a chip IC of claim 17 wherein the warm boot procedure further includes disabling the power-off timer.
26. A method for booting a system on a chip integrated circuit (IC), the method comprising:
reading a warm boot flag stored in a persistent register of an analog portion of the system on a chip IC, the analog portion including a power-off timer; and
executing a warm boot procedure when the warm boot flag is set, wherein the warm boot procedure includes reading a memory index from the persistent register and programming a memory controller with the memory index, wherein the memory index is an index to a table for memory parameters that correspond to an external memory device.
27. The method for booting a system on a chip IC of claim 26 wherein the table for memory parameters that correspond to the external memory device is a read-only memory (ROM) table.
28. The method for booting the system on a chip IC of claim 26 further comprising:
executing a cold boot procedure when the warm boot flag is not set.
29. The method for booting the system on a chip IC of claim 26 wherein the warm boot procedure further includes retrieving from a read only memory device at least one of: a memory timing parameter, and a memory size parameter.
30. The method for booting the system on a chip IC of claim 26 wherein the warm boot procedure further includes changing a memory device from a low power state to an active state.
31. The method for booting the system on a chip IC of claim 26 wherein the warm boot procedure further includes loading a jump address stored in a jump vector and jumping to a warm boot code section stored in a memory device beginning at the jump address.
32. The method for booting the system on a chip IC of claim 31 wherein the warm boot procedure further includes copying a portion of the memory device to an on-chip memory.
33. The method for booting the system on a chip IC of claim 26 wherein the warm boot procedure further includes disabling the power-off timer.
34. The method for booting a system on a chip IC of claim 26 further comprising:
determining if the power-off timer has expired; and
executing a power-off routine when the power-off timer has expired.