Integrated circuit analysis method and program product
View Patent ↗A method for analyzing integrated circuits (IC's) has steps of dividing the circuit into a plurality of individual blocks that are linked together. Each block is comprised of a plurality of latches and paths connecting the latches. The blocks are compressed by removing all detail not required for performing global transparency timing modeling.
1. A method for making an integrated circuit model for an integrated circuit comprising the steps of:
dividing the integrated circuit into a plurality of connected blocks, each block having a plurality of latches, at least one of said latches on each of said blocks having a global path connected to a latch from a second of said plurality of blocks;
compressing each of said blocks by removing all of said latches from each of said blocks not required for modeling global transparency;
identifying said latches in each of said blocks that are connected to more than one incoming global path; and
creating a clone latch for each of said incoming global paths greater than one for each of said identified latches, moving one of said incoming global paths from each of said identified latches to one of said clone latches whereby each of said identified latches and each of said clone latches are connected to one incoming global path.
2. A method for making an integrated circuit model as in claim 1 , wherein the method further comprises the step of pruning the integrated circuit model by removing from each latch all incoming paths except for the path having the greatest delay.
3. A computer program product for modeling an integrated circuit comprising computer executable instructions stored in a computer readable medium that when executed cause a computer to:
divide the integrated circuit into a plurality of connected blocks, each block having a plurality of latches, at least one of said latches on each of said blocks having a global path connected to a latch from a second of said plurality of blocks, each of said latches in each of said blocks having at least one internal path connected to others of said latches in said block;
compress each of said blocks by removing all of said latches not required for modeling global transparency
identify said latches in each of said blocks that are connected to more than one incoming global path;
create a clone latch for each of said incoming global paths greater than one for each of said identified latches, move one of said incoming global paths from each of said identified latches to one of said clone latches whereby each of said identified latches and each of said clone latches are connected to one incoming global path; and
prune the integrated circuit model by removing all incoming paths to each latch except for the path having the largest delay.
4. A computer program product for modeling an integrated circuit comprising computer executable instructions stored on a computer readable medium that when executed cause a computer to:
divide the integrated circuit into a plurality of connected blocks, each block having a plurality of latches, at least one of said latches on each of said blocks having a global path connected to a latch from a second of said plurality of blocks, each of said latches in each of said blocks having at least one internal path connected to others of said latches in said block, each of said paths having a gate delay equal to the sum of the delays for all gates along said path, each of said internal paths having a wire delay, at least a first of said latches being connected to an incoming global path;
compress each of said blocks by calculating a representative path delay for each path using said gate delays and said wire delays, remove latches for each of said blocks not required for modeling global transparency, pruning said blocks by removing all incoming internal paths for each of said latches in each of said blocks except for said incoming path resulting in the largest path delay, identify said latches in each of said blocks that are connected to more than one incoming global path, create a clone latch for each of said incoming global paths greater than one for each of said identified latches, move one of said incoming global paths from each of said identified latches to one of said clone latches whereby each of said identified latches and each of said clone latches are connected to one incoming global path.