IP Library Granted Patent US 7,286,008
Granted Patent B2
US 7,286,008 · App. 11/262,512 · Granted Oct 23, 2007

Digital amplifier

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Quick Facts
Patent No.
US 7,286,008
App. No.
11/262,512
Granted
Oct 23, 2007
Kind
B2
Abstract

A digital amplifier ( 1 ) comprising a first modulation stage ( 9 ) arranged to receive a digital data signal and to generate a corresponding modulated reference signal; a comparator ( 12 ) arranged to receive a feedback signal and the modulated reference signal and generate a corresponding error signal ( 13 ) indicative of a difference between the modulated reference signal and the feedback signal; an integration stage ( 44 ) arranged to integrate the error signal ( 13 ) from the comparator ( 12 ) to generate an integrated digital error signal; a summer ( 19 ) arranged to receive the integrated digital error signal and the digital data signal ( 8 ) and generate an adjusted digital data signal indicative of their sum; an output stage comprising a second modulation stage, the output stage being arranged to receive the adjusted digital data signal and to generate a corresponding modulated output signal for driving a load ( 7 ); and a feedback circuit arranged to provide said feedback signal to the comparator ( 12 ), the feedback signal being indicative of the modulated output signal.

Claims (31)

1. A digital amplifier comprising:

a first modulation stage arranged to receive a digital data signal and to generate a corresponding modulated reference signal;

a comparator arranged to receive a feedback signal and the modulated reference signal and generate a corresponding error signal indicative of a difference between the modulated reference signal and the feedback signal;

an integration stage arranged to integrate the error signal from the comparator to generate an integrated digital error signal;

a summer arranged to receive the integrated digital error signal and the digital data signal and generate an adjusted digital data signal indicative of their sum;

an output stage comprising a second modulation stage, the output stage being arranged to receive the adjusted digital data signal and to generate a corresponding modulated output signal for driving a load; and

a feedback circuit arranged to provide said feedback signal to the comparator, the feedback signal being indicative of the modulated output signal.

2. A digital amplifier according to claim 1 , wherein the integration stage comprises at least three integrators arranged to provide at least third order integration of the error signal.

3. A digital amplifier according to claim 1 , wherein the second modulation stage operates at a switching frequency within the range 0 Hz-4 MHz.

4. A digital amplifier according to claim 1 , further comprising a digital noise shaper adapted to receive a digital input signal and to noise-shape said digital input signal and provide the noise-shaped signal to the first modulation stage as said digital data signal.

5. A digital amplifier according to claim 1 , wherein the first modulation stage comprises a pulse width modulator and the modulated reference signal is a pulse width modulated signal.

6. A digital amplifier according to claim 1 , wherein the second modulation stage comprises a pulse width modulator and the modulated output signal is a pulse width modulated signal.

7. A digital amplifier according to claim 1 , wherein the first modulation stage comprises a modulator, arranged to receive the digital data signal, and an inverter arranged to invert the modulator output.

8. A digital amplifier according to claim 1 , wherein said second modulation stage is arranged to generate a modulated control signal corresponding to the adjusted digital data signal, and the output stage further comprises a switching circuit arranged so as to be controlled by the modulated control signal.

9. A digital amplifier according to claim 1 , wherein said modulated output signal is a modulated output voltage for application to one side of a load.

10. A digital amplifier according to claim 1 , wherein the integration stage comprises a first analogue integrator arranged to integrate the error signal, an analogue to digital converter (ADC) arranged to convert an analogue output of the first analogue integrator to a digital signal, and two digital integrators arranged in series to integrate the digital signal from the ADC.

11. A digital amplifier according to claim 1 , wherein the integration stage comprises at least three digital integrators.

12. A digital amplifier according to claim 1 , wherein the integration stage comprises at least one analogue integrator, an analogue to digital converter, and at least one digital integrator.

13. A digital amplifier according to claim 12 , wherein the integration stage comprises at least two digital integrators.

14. A digital amplifier according to claim 10 , wherein the analogue to digital converter provides at least 10 bit resolution.

15. A digital amplifier according to claim 14 , wherein the analogue to digital converter provides at least 14 bit resolution.

16. A digital amplifier according to claim 1 , wherein the modulated output signal is a modulated voltage, and the feedback circuit comprises a voltage divider, arranged such that the feedback signal is a voltage signal proportional to said output voltage.

17. A digital amplifier according to claim 1 , wherein the modulated output signal is a modulated output voltage for application to one side of a load, the amplifier further comprising:

an inverter arranged to invert the digital data signal

a third modulation stage arranged to receive the inverted digital data signal and to generate a corresponding second modulated reference signal;

a second comparator arranged to receive a second feedback signal and the second modulated reference signal and generate a corresponding second error signal indicative of a difference between the second modulated reference signal and the second feedback signal;

a second integration stage arranged to integrate the second error signal from the second comparator to generate a second integrated digital error signal;

a second summer arranged to receive the second integrated digital error signal and the inverted digital data signal and generate a second adjusted digital data signal indicative of their sum;

a second output stage comprising a fourth modulation stage, the second output stage being arranged to receive the second adjusted digital data signal and to generate a corresponding second modulated output signal for driving a load; and

a second feedback circuit arranged to provide said second feedback signal to the second comparator, wherein the second modulated output signal is a second modulated voltage for application to a second side of the load, and the second feedback signal is indicative of the second modulated voltage.

18. A digital amplifier according to claim 17 , wherein the first and second output stages comprise an H-bridge circuit for driving an output load.

Assignments (7)
CHANGE OF NAME Recorded Sep 22, 2015
From: CAMBRIDGE SILICON RADIO LIMITED
To: QUALCOMM TECHNOLOGIES INTERNATIONAL, LTD.
Reel/Frame 036663/0211 →
CHANGE OF NAME Recorded Jan 28, 2013
From: ZETEX SEMICONDUCTORS PLC
To: DIODES ZETEX SEMICONDUCTORS LIMITED
Reel/Frame 029706/0016 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2013
From: L&R W LIMITED; WATTS, ROBERT
To: DIODES ZETEX SEMICONDUCTORS LIMITED
Reel/Frame 029706/0341 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2013
From: DIODES ZETEX SEMICONDUCTORS LIMITED
To: CAMBRIDGE SILICON RADIO LIMITED
Reel/Frame 029706/0432 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 21, 2012
From: DIODES ZETEX SEMICONDUCTORS LIMITED
To: CAMBRIDGE SILICON RADIO LIMITED
Reel/Frame 029027/0060 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2012
From: DIODES ZETEX SEMICONDUCTORS LIMITED
To: CAMBRIDGE SILICON RADIO LIMITED
Reel/Frame 029017/0689 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2006
From: WATTS, ROBERT
To: ZETEX SEMICONDUCTORS PLC
Reel/Frame 018055/0719 →