Methods of fabricating integrated circuit transistors by simultaneously removing a photoresist layer and a carbon-containing layer on different active areas

1. A method of fabricating integrated circuit transistors comprising:

forming on an integrated circuit substrate, a first active area including a first insulated gate thereon and a second active area including a second insulated gate thereon;

sequentially blanket forming on both the first and second active areas, a nitride stress-generating layer, a carbon-containing layer, an etch stop layer and a photoresist layer;

selectively removing the photoresist layer from the etch stop layer on the second active area to expose the etch stop layer on the second active area while retaining at least some of the photoresist layer on the etch stop layer on the first active area;

removing the etch stop layer that is exposed on the second active area;

etching the photoresist layer on the first active area to expose the etch stop layer on the first active area while simultaneously etching the carbon-containing layer on the second active area to expose the nitride stress-generating layer on the second active area;

removing the etch stop layer that is exposed on the first active area to expose the carbon-containing layer on the first active area;

removing the nitride stress-generating layer that is exposed on the second active area;

implanting dopants into the second active area to form source/drain regions in the second active area while simultaneously blocking implantation of the dopants into the nitride stress-generating layer on the first active area by the carbon-containing layer on the first active area;

removing the carbon-containing layer from the nitride stress-generating layer on the first active area;

annealing to memorize stress in the first active area that is generated by the nitride stress-generating layer thereon; and

removing the nitride stress-generating layer from the first active area.

2. A method according to claim 1 wherein the carbon-containing layer comprises an amorphous carbon layer.

3. A method according to claim 1 wherein the carbon-containing layer comprises an organic top-coating material for photoresist.

4. A method according to claim 1 wherein forming on an integrated circuit substrate, a first active area including a first insulated gate thereon and a second active area including a second insulated gate thereon comprises forming on the integrated circuit substrate, the first active area including a first insulated gate thereon, source/drain regions on opposite sides and spaced apart from the first insulated gate and extension regions between the source/drain regions and the first insulated gate, and a second active area including a second insulated gate thereon and first and second extension regions on opposite sides of the second insulated gate.

5. A method according to claim 1 wherein removing the etch stop layer that is exposed on the first active area to expose the carbon-containing layer on the first active area and removing the nitride stress-generating layer that is exposed on the second active area are performed simultaneously.

6. A method according to claim 1 wherein the first active area is an NFET active area and the second active area is a PFET active area.

7. A method according to claim 1 wherein sequentially blanket forming is preceded by forming an oxide layer on the first and second active areas.

8. A method according to claim 3 wherein the organic top-coating material for photoresist comprises NFC top-coating material marketed by Japan Synthetic Rubber (JSR).

9. A method of fabricating integrated circuit transistors comprising:

forming on an integrated circuit substrate, a first active area including a first insulated gate thereon and a second active area including a second insulated gate thereon;

sequentially blanket forming on both the first and second active areas, a nitride stress-generating layer, a carbon-containing layer and a photoresist layer;

selectively removing the photoresist layer on the second active area while retaining at least some of the photoresist layer on the first active area;

etching the photoresist layer on the first active area while simultaneously etching the carbon-containing layer on the second active area;

removing the nitride stress-generating layer on the second active area;

implanting dopants into the second active area to form source/drain regions in the second active area while simultaneously blocking implantation of the dopants into the nitride stress-generating layer on the first active area by the carbon-containing layer on the first active area;

removing the carbon-containing layer from the nitride stress-generating layer on the first active area;

annealing to memorize stress in the first active area that is generated by the nitride stress-generating layer thereon; and

removing the nitride stress-generating layer from the first active area.

10. A method according to claim 9 wherein the carbon-containing layer comprises an amorphous carbon layer.

11. A method according to claim 9 wherein the carbon-containing layer comprises an organic top-coating material for photoresist.

12. A method according to claim 9 wherein forming on an integrated circuit substrate, a first active area including a first insulated gate thereon and a second active area including a second insulated gate thereon comprises forming on the integrated circuit substrate, a first active area including first insulated gate thereon, source/drain regions on opposite sides and spaced apart from the first insulated gate and extension regions between the source/drain regions and the first insulated gate, and a second active area including a second insulated gate thereon and first and extension regions on opposite sides of the second insulated gate.

13. A method according to claim 9 wherein the first active area is an NFET active area and the second active area is a PFET active area.

14. A method according to claim 11 wherein the organic top-coating material for photoresist comprises NFC top-coating material marketed by Japan Synthetic Rubber (JSR).

15. A method of fabricating integrated circuit transistors comprising:

simultaneously removing a photoresist layer on a first active area of an integrated circuit substrate and a carbon-containing layer on a second active area of the integrated circuit substrate to expose a nitride stress-generating layer on the second active area;

removing the nitride stress-generating layer on the second active area;

implanting dopants into the second active area to form source/drain regions in the second active area while simultaneously blocking implantation of the dopants into the nitride stress-generating layer on the first active area by the carbon-containing layer on the first active area;

removing the carbon-containing layer from the nitride stress-generating layer on the first active area;

annealing to memorize stress in the first active area that is generated by the nitride stress-generating layer thereon; and

removing the nitride stress-generating layer from the first active area.

16. A method of fabricating integrated circuit transistors comprising:

simultaneously removing a photoresist layer on a first active area of an integrated circuit substrate and a carbon-containing layer on a second active area of the integrated circuit substrate to expose a nitride stress-generating layer on the second active area;

wherein the carbon-containing layer comprises an organic top-coating material for photoresist; and

wherein the organic top-coating material for photoresist comprises NFC top-coating material marketed by Japan Synthetic Rubber (JSR).