Method, apparatus and computer program product for implementing scan-chain-specific control signals as part of a scan chain
View Patent ↗A method, apparatus and computer program product are provided for implementing scan-chain-specific control signals as an integral part of a scan chain. A scan input vector including scan data input and a scan control signal is applied to a register latch that forms the scan chain. The register latch includes a logic gate for combining a global clock control (THOLD) signal and the scan control signal. The scan control signal is routed around the register latch and including in a scan output vector including scan data output. Chain-specific control signals are eliminated from a clock control signal distribution tree used with the scan chain of the invention.
1. A method for implementing scan-chain-specific control signals as an integral part of a scan chain formed by a plurality of register latches, said method comprising the steps of:
applying a scan data input bit and a chain-specific scan control signal bit to a register latch;
providing the register latch with a logic gate for combining a global clock control signal and the chain-specific scan control signal bit;
routing the chain-specific scan control signal bit around the register latch for combining a scan data output bit of the register latch and the scan control signal bit; and
providing a clock control signal distribution tree used with the scan chain with said clock control signal distribution tree being implemented independently of the chain-specific scan control signal bit.
2. The method for implementing scan-chain-specific control signals as recited in claim 1 wherein said global clock control signal includes a global clock signal.
3. The method for implementing scan-chain-specific control signals as recited in claim 1 includes eliminating chain-specific control signals from a clock control signal distribution tree used with the scan chain.
4. The method for implementing scan-chain-specific control signals as recited in claim 1 wherein the step of applying a scan data input bit and a scan control signal bit to the register latch includes providing a plurality of bits N including one bit for said scan data input bit and N-1 bits for each of a plurality of the chain-specific scan control signal bit of a plurality of chain-specific control signals.
5. The method for implementing scan-chain-specific control signals as recited in claim 1 wherein the step of providing the register latch with said logic gate includes providing an AND gate for receiving said chain-specific scan enable control signal bit and the global clock control signal.
6. The method for implementing scan-chain-specific control signals as recited in claim 4 includes providing a global clock control staging latch coupled to an output of said AND gate.
7. The method for implementing scan-chain-specific control signals as recited in claim 1 wherein the step of applying a scan data input bit and a chain-specific scan control signal bit to the register latch includes providing a logic built-in self-test (LBIST) engine for providing the scan data input bit to the scan chain; and said LBIST engine for receiving said chain-specific scan control signal bit from the scan chain.