Low noise op amp
View Patent ↗An analog circuit for processing analog signals in an integrated circuit comprising a number of metal oxide semiconductor transistor devices. The circuit includes a first transistor device having a thin oxide thickness, and a second transistor device having a thicker oxide thickness. A voltage pulse protection is arranged to maintain the operating voltage of the thin oxide transistor in the presence of a rapidly rising voltage waveform (e.g. ESD), or at least to mitigate its effect on the thin oxide transistor device. Preferably a cascode based op amp structure is implemented.
1. An analog circuit for processing analog signals in an integrated circuit comprising a number of metal oxide semiconductor transistor devices, the circuit comprising: a first said transistor device having a first oxide thickness, and arranged in use to have an operating voltage below a predetermined level; a second said transistor device having a greater oxide thickness and arranged such that in use it is not constrained by the predetermined operating voltage level; and voltage pulse protection means arranged to substantially maintain said operating voltage in the presence of a rapidly rising voltage waveform applied to the first transistor device.
2. A circuit according to claim 1 , wherein the voltage pulse protection means is a discrete device coupled across the first transistor device.
3. A circuit according to claim 2 , wherein the discrete device is a capacitor.
4. A circuit according to claim 2 , wherein the voltage pulse protection means is coupled across the first transistor device to the gate connection of the second transistor device.
5. A circuit according to claim 1 , comprising a plurality of first and second transistor devices each arranged into a circuit stage and each comprising a voltage pulse protection means coupled across said respective first transistor device.
6. A circuit according to claim 1 , wherein the predetermined operating voltage level is 3.6V and the first oxide thickness is 70 nm.
7. A circuit according to claim 1 , wherein the second transistor device forms part of a cascode transistor device circuit within said analog circuit.
8. A circuit according to claim 7 , wherein the cascode transistor device circuit is a differential folded cascode op amp circuit.
9. A circuit according to claim 8 , wherein the op amp circuit further comprises input, bias, current mirror and constant current sub-circuits and wherein said first transistor device forms part of one of said op amp sub-circuits.
10. A circuit according to claim 1 , further comprising a clamp circuit arranged to limit the operating voltage of said first transistor to the predetermined operating voltage level.
11. A mixed signal integrated circuit, comprising an analog circuit according to claim 1 .
12. A method of processing an analog signal, comprising applying the analog signal to an analog circuit for processing analog signals in an integrated circuit comprising a number of metal oxide semiconductor transistor devices, the analog circuit comprising a first said transistor device having a first oxide thickness, and a second said transistor device having a greater oxide thickness, such that the analog signal is processed by both said transistor devices; wherein the first transistor device is arranged to have an operating voltage below a predetermined level and wherein the second transistor device is arranged such that it is not constrained by the predetermined operating voltage level; and wherein a voltage pulse protection means is arranged to substantially maintain said operating voltage in the presence of a rapidly rising voltage waveform applied to the first transistor device.
13. A method according to claim 12 , wherein the voltage pulse protection means is a discrete device coupled across the first transistor device.
14. A method according to claim 13 , wherein the discrete device is a capacitor.
15. A method according to claim 12 , wherein the second transistor device forms part of a cascode transistor device circuit within said analog circuit.
16. A method according to claim 13 , wherein the second transistor device forms part of a cascode transistor device circuit within said analog circuit.
17. A method according to claim 14 , wherein the second transistor device forms part of a cascode transistor device circuit within said analog circuit.
18. A circuit according to claim 3 , wherein the voltage pulse protection means is coupled across the first transistor device to the gate connection of the second transistor device.