Granted Patent B1

US 7,554,843 · App. 11/267,460 · Granted Jun 30, 2009

Abstract

Claims (60)

1. A serial interface apparatus comprising:

a first and second input;

the second input comprising a logic level signal and a non-logic level signal coupling to the input of a level shifter; and

the second input also coupling to a location requiring a non-logic level signal;

wherein the non-logic level signal comprises a voltage different from a logic level signal;

wherein on the second input, a first part of communication comprises one or more logic level pulses, and a second part of communication comprises one or more non-logic level pulses;

wherein on the second input, the non-logic level signal and the logic level signal provide different functions.

2. The serial interface of claim 1 wherein the logic level signal is either a clock or a serial data signal, and the non-logic signal is capable of performing a write operation in a non-volatile memory.

3. The serial interface of claim 1 wherein the serial interface comprises a bus interface logic for providing logic level data, control, and synchronization to the location requiring the voltage different from that of the logic level.

4. The serial interface of claim 3 wherein the first input couples directly to the bus interface logic.

5. The serial interface of claim 1 , wherein the location requiring the voltage different from that of the logic level comprises a memory, a device, a peripheral, a card, a cable or a display.

6. A method for combining logic level signals with non-logic level signals in a serial interface comprising the steps:

sending a first logic level signal on a first input;

sending a non-logic level signal and a second logic level signal on a second input; and

converting the non-logic level and the second logic signal on the second input to a third logic level signal using a level shifter;

combining the first logic level signal and the third logic level signal in bus interface logic,

wherein the non-logic level signal comprises a voltage different from a logic level;

wherein on the second input, a first part of communication comprises one or more logic level pulses, and a second part of communication comprises one or more non-logic level pulses;

wherein the first logic level signal, the second logic level signal and the non-logic level signal provide different functions.

7. The method of claim 6 wherein a bus interface logic using the first and second logic level signals provides data to and controls a location requiring a non-logic level signal.

8. The method of claim 6 wherein the location requiring a non-logic level signal comprises a memory, a device, a peripheral, a card, a cable or a display.

9. The method of claim 6 wherein the first logic level signal is either a clock or a serial data signal, and the second logic level signal is the other signal, and the non-logic signal is capable of performing a write operation in a non-volatile memory.

10. A method of serial communication comprising the steps:

converting a non-logic level signal to a logic level signal using a level shifter producing a logic level reset signal;

sending logic level input data; and

sending one or more non-logic level voltage pulses on either a logic level clock input or a logic level serial data input to a location requiring the non-logic level voltage;

wherein the logic level signal is a two level logic signal.

11. The method of claim 10 wherein one or more non-logic level voltage pulses are used to program or erase one or more bits.

12. The method of claim 10 wherein the location requiring the non-logic level voltage comprises a non-volatile memory.

13. The method of claim 12 wherein the non-volatile memory is implemented using Fowler-Nordheim tunneling, Channel Hot Electron injection, or a combination thereof.

14. The method of claim 10 wherein the non-logic level voltage pulses are followed by sending a reset signal.

15. A serial interface for an analog non-volatile memory apparatus comprising:

a first and second input;

the second input comprising a logic level signal and a non-logic level signal coupling to the input of a level shifter; and

the second input also coupling to a location requiring a voltage different from a logic level;

wherein on the second input, a first part of communication comprises one or more logic level pulses, and a second part of communication comprises one or more non-logic level pulses;

wherein on the second input, the non-logic level signal and the logic level signal provide different functions.

16. The serial interface of claim 15 wherein the serial interface comprises a bus interface logic which controls and provides data to the analog non-volatile memory apparatus.

17. The serial interface of claim 15 wherein the non-volatile memory produces a set of one or more analog outputs.

18. The serial interface of claim 17 wherein the analog outputs can be read, erased, and programmed by an external system.

19. The serial interface of claim 17 wherein the analog outputs are coupled to a multiplexer coupling one of the analog outputs to an output pin.

20. The serial interface of claim 19 wherein the bus interface logic generates a signal that determines the output signal sent to the output pin.

21. The serial interface of claim 18 wherein the external system uses one or more high voltage pulses to erase and program the analog outputs.

22. The serial interface of claim 17 wherein the analog outputs are coupled to a multiplexer coupling one of analog outputs to a second multiplexer under control of the interface and the second multiplexer is coupled to the first input such that when a direction control signal changes state, a selected analog output from the analog outputs is transferred onto the first input.

23. A method of serial communication to program or erase an analog output of a non-volatile memory comprising the steps:

converting a non-logic level signal to a logic level signal using a level shifter;

producing a logic level reset signal;

sending logic level input data; and

sending one or more non-logic level voltage pulses on either a logic level clock input or a logic level serial data input to a location requiring the non-logic level voltage;

wherein the logic level signal is a two level logic signal.

24. The method of claim 23 wherein the non-logic level voltage pulses are followed by sending a reset signal.

25. The method of claim 23 wherein the clock input or the data input coupling to the level shifter converts the non-logic voltage signal to a logic level signal for a bus interface logic which provides the data to and controls the analog output of the non-volatile memory.

26. A two wire serial interface bus comprising:

a first wire and a second wire;

the first wire comprises a first logic level signal; and

the second wire comprises a non-logic level signal, and a second logic level signal, wherein the second wire is coupled to a level shifter and is also coupled to a location requiring a non-logic level signal; and

a bus interface logic whose inputs are coupled from the output of the level shifter and from the first wire, the bus interface logic provides data and control information;

wherein on the second input, a first part of communication comprises one or more logic level pulses, and a second part of communication comprises one or more non-logic level pulses;

wherein the first logic level signal is either a clock signal or a serial data signal and the second logic level signal is the other signal;

wherein the non-logic level signal is capable of performing a write operation in a non-volatile memory.

Assignments (9)