Two step data analysis
View Patent ↗A data analyzer for analyzing an incoming data stream, comprising a pattern matcher adapted for comparing in a first step the first data stream with a first data pattern and in a second step a second data stream with a second data pattern and for generating a match signal indicative of a match between the first data stream and the first data pattern or between the second data stream and the second data pattern, a trace memory adapted for storing a part of the first data stream dependent on the match signal of the first step, and for outputting stored data as second data stream in a second step and a data switch adapted for receiving the first data stream and the second data stream, and to be set in the first step to a first state for providing the pattern matcher with the first data stream and in the second step to a second state for providing the pattern matcher with the second data stream.
1. A data analyzer for analyzing a incoming first data stream provided by a data source, comprising:
a pattern matcher adapted for comparing in a first step the first data stream with a first data pattern and in a second step a second data stream with a second data pattern and for generating a match signal indicative of a match between the first data stream and the first data pattern or between the second data stream and the second data pattern,
a trace memory adapted for storing a part of the first data stream dependent on the match signal of the first step, and for outputting stored data as second data stream in a second step and
a data switch adapted for receiving the first data stream and the second data stream, and to be set in the first step to a first state for providing the pattern matcher with the first data stream and in the second step to a second state for providing the pattern matcher with the second data stream.
2. The analyzer of claim 1 , comprising a controller that is adapted to control the pattern matcher, the trace memory and the data switch for initiating the first and second steps.
3. The analyzer of claim 2 , wherein the controller is adapted to control:
in the first step setting the data switch to the first state, setting the pattern matcher to the first data pattern and activating the trace memory for storing the part of the incoming data stream, and
in the second step setting the data switch to the second state, setting the pattern matcher to the second data pattern, activating the trace memory to output the second stream.
4. The analyzer of claim 2 , wherein the controller comprises a user interface that is adapted to at least one of: entering the data patterns and initiating the first and second step.
5. The analyzer of claim 2 , wherein the controller is adapted for repeating the second step with each a different data pattern to be loaded to the pattern matcher.
6. The analyzer of claim 5 , wherein a counter is comprised adapted four counting the trigger signal occurrences for each of the different data patterns.
7. The analyzer of claim 1 , comprising one or more further pattern matchers that are adapted for receiving the data stream in parallel and for generating each a match signal dependent on each an activated data pattern.
8. The analyzer of claim 7 , further comprising a trigger circuit adapted for generating a trigger signal on the base of said match signals to be provided to the trace memory for storing a selected part of the first data stream.
9. The analyzer of claim 8 , wherein the trigger circuit comprising a state machine that is adapted for determining an actual state on the base of the match signals and a previous state, and generating the trigger signal further dependent on actual state.
10. The analyzer of claim 7 , further comprising a run control circuit that is adapted for generating a trace memory control signal depending on the trigger signal received from the trigger circuit to control the trace memory such that the trigger memory stops the data acquisition after one of: a pre-defined time and a pre-defined amount of received data.
11. The analyzer of claim 1 , wherein the incoming data stream, the second data stream are sequences of data of a plurality of parallel bits.
12. The analyzer of claim 1 , comprising a second trace memory that is connected over a controllable connection to the first trace memory and wherein the controllable connection is adapted to be controlled by the trigger circuit such that selected data of the second data stream is stored in the second trace memory.
13. A method of analyzing a first data stream, comprising the steps of:
providing a pattern matcher with a first data stream for comparing the first data stream with a first data pattern and generating a match signal indicative of a match between the first data stream and the first data pattern,
storing in a trace memory a part of the first data stream dependent on the match signal and outputting stored data as second data stream and
providing the pattern matcher with the second data stream for comparing the second data stream with a second data pattern and generating a match signal indicative of a match between the second data stream and the second data pattern.
14. A software program or product, preferably stored on a data carrier, for controlling the following steps, when run on a data processing system of the analyzer:
providing a pattern matcher with a first data stream for comparing the first data stream with a first data pattern and generating a match signal indicative of a match between the first data stream and the first data pattern,
storing in a trace memory a part of the first data stream dependent on the match signal and outputting stored data as second data stream and
providing the pattern matcher with the second data stream for comparing the second data stream with a second data pattern and generating a match signal indicative of a match between the second data stream and the second data pattern.