IP Library Granted Patent US 7,491,559
Granted Patent B2
US 7,491,559 · App. 11/270,373 · Granted Feb 17, 2009

Low-temperature polysilicon display and method for fabricating same

Assignee: AU Optronics Corporation
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Quick Facts
Patent No.
US 7,491,559
App. No.
11/270,373
Granted
Feb 17, 2009
Kind
B2
Abstract

A display panel comprising at least one display area and one peripheral circuit area having electronic components for driving the display components in the display area. The electronic components in the display area are fabricated substantially on a polysilicon layer converted from amorphous silicon by a solid phase crystallization process, whereas the electronic components in the peripheral circuit area are fabricated substantially on a polysilicon layer converted from amorphous silicon first by the solid phase crystallization process and then by laser annealing. As such, display area has a more uniform poly-Si layer substantially free of defects associated with laser annealing, and the peripheral circuit has a poly-Si layer with higher electron mobility.

Claims (31)

1. A method for producing a display panel on a substrate having a first area and a second area, the display panel having a display area in the first area and an electronic circuit area in the second area electrically connected to the display area, the display area comprising display components, the electronic circuit area comprising electronic components, said method comprising the steps of:

disposing an amorphous silicon layer on the substrate;

converting the amorphous silicon layer in both the first and second areas into substantially a poly-silicon layer by a solid-phase cystallization process;

further annealing the poly-silicon layer in the second area by a laser beam for providing a further annealed poly-silicon layer;

fabricating the display components in the poly-silicon layer in the first area;

fabricating the electronic components in the further annealed poly-silicon layer in the second area; and

providing electrical connections between the display area and the electronic circuit area.

2. The method of claim 1 , further comprising the step of providing a buffer layer on the substrate before carrying out the disposing step.

3. The method of claim 1 , wherein the poly-silicon layer in the first area has an electron mobility smaller than 70 cm 2 /Vsec and the further annealed poly-silicon layer in the second area has an electron mobility equal to or greater than 70 cm 2 /Vsec.

4. The method of claim 1 , wherein the display components in the first area comprise organic light-emitting elements.

5. The method of claim 1 , wherein the electronic components in the second area comprise one or more integrated circuits for providing data signals to the display area.

6. The method of claim 1 , wherein the display area comprises display elements arranged in a two-dimensional array, and wherein the electronic components in the second area comprise one or more integrated circuits for providing scanning signals to the array.

7. The method of claim 1 , wherein the electronic components in the second area comprise a plurality of thin-film transistors.

8. The method of claim 1 , wherein the substrate comprises a glass substrate.

9. The method of claim 4 , wherein the display components in the first area further comprise switching elements for controlling the organic light-emitting elements.

10. The method of claim 9 , wherein the switching elements comprise thin-film transistors.

11. A display panel comprising:

a substrate having a first area and a second area;

a display area in the first area, the display area comprising display components, wherein at least some of the display components are made of poly-silicon having an electron mobility smaller than 70 cm 2 /Vsec;

an electronic circuit area in the second area, the electronic circuit area comprising electronic components, wherein at least some of the electronic components are made of poly-silicon having an electron mobility greater than or equal to 70 cm 2 /Vsec; and

electrical connectors connecting the electronic area to the display area.

12. The display panel of claim 11 , wherein said display components in the first area are made of poly-silicon having a first grain size and electronic components in the second area are made of poly-silicon having a second grain size larger than the first gain size.

13. The display panel of claim 11 , wherein the display components in the first area comprise organic light-emitting elements.

14. The display panel of claim 11 , wherein the electronic components in the second area comprise one or more integrated circuits for providing data signals to the display area.

15. The display panel of claim 11 , wherein the display area comprises a plurality of display elements arranged in a two-dimensional array, and wherein the electronic components in the second area comprise one or more integrated circuits for providing scanning signals to the array.

16. The display panel of claim 11 , wherein the electronic components in the second area comprise a plurality of thin-film transistors.

17. The display panel of claim 11 , wherein the substrate comprises a glass substrate.

18. The display panel of claim 11 , wherein the poly-silicon in the first area is converted from amorphous silicon in a solid-phase crystallization process.

19. The display panel of claim 11 , wherein the poly-silicon in the second area is converted from amorphous silicon in a solid-phase crystallization process and further in a laser annealing process.

20. The display panel of claim 13 , wherein the display components in the first area further comprise switching elements for controlling the organic light-emitting elements.

21. The display panel of claim 20 , wherein the switching elements comprise thin-film transistors.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2023
From: AUO CORPORATION
To: OPTRONIC SCIENCES LLC
Reel/Frame 064658/0572 →
CHANGE OF NAME Recorded May 25, 2023
From: AU OPTRONICS CORPORATION
To: AUO CORPORATION
Reel/Frame 063785/0830 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2005
From: PENG, CHIA-TIEN
To: AU OPTRONICS CORPORATION
Reel/Frame 017212/0206 →
Continuity (1)
Related Publication 20070105287A1 · May 10, 2007