Integrated circuit device and electronic instrument

1. An integrated circuit device, comprising:

a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and

a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block,

the data line driver block including first to Nth (N is an integer larger than one) divided data line driver blocks, each of the first to Nth divided data line driver blocks driving a different data line group of the data line groups,

the wordline control circuit driving an identical wordline N times from among the wordlines in one horizontal scan period of the display panel, and

the first to Nth divided data line driver blocks being disposed along a first direction in which the bitlines extend.

2. The integrated circuit device as defined in claim 1 ,

including first to Nth latch signals supplied to the first to Nth divided data line driver blocks, respectively, and

the first to Nth divided data line driver blocks latching data supplied from the RAM block based on the first to Nth latch signals.

3. The integrated circuit device as defined in claim 2 ,

when the identical wordline is selected first time, the first latch signal is set to active so that data supplied from the RAM block in response to the first selection is latched by the first divided data line driver block, and

when the identical wordline is selected Kth time (1≦K≦N; K is an integer), the Kth latch signal is set to active so that data supplied from the RAM block in response to the Kth selection is latched by the Kth divided data line driver block.

4. The integrated circuit device as defined in claim 2 ,

the RAM block including a sense amplifier circuit which outputs M-bit data (M is an integer larger than one) upon one wordline selection,

at least M×N memory cells being arranged in the RAM block along a second direction in which the wordlines extend, and

(M×N)-bit data being supplied to the sense amplifier circuit upon one wordline selection.

5. The integrated circuit device as defined in claim 4 ,

the sense amplifier circuit detecting and outputting M-bit data of the (M×N)-bit data based on a sense amplifier select signal.

6. The integrated circuit device as defined in claim 5 ,

the sense amplifier circuit including a plurality of selective sense amplifiers, and

each time the identical wordline is selected N times in the one horizontal scan period, each of the selective sense amplifiers receives N-bit data from first to Nth memory cells of M×N memory cells connected with the selected wordline, and detects and outputs 1-bit data from a Kth (1≦K≦N; K is an integer) memory cell of the first to Nth memory cells based on the sense amplifier select signal.

7. The integrated circuit device as defined in claim 6 ,

the sense amplifier select signal being set so that the selective sense amplifier detects and outputs data received from the first memory cell when the identical wordline is selected first time, and detects and outputs data received from the Kth memory cell when the identical wordline is selected Kth time.

8. The integrated circuit device as defined in claim 4 ,

each of the first to Nth divided data line driver blocks driving one of the data line groups based on the M-bit data supplied from the RAM block, and

when a grayscale of a pixel corresponding to a data line is G bits, each of the first to Nth divided data line driver blocks drives M/G data lines.

9. The integrated circuit device as defined in claim 4 ,

each of the first to Nth divided data line driver blocks driving one of the data line groups based on the M-bit data supplied from the RAM block, and

when a grayscale of a pixel corresponding to a data line is G bits, each of the first to Nth divided data line driver blocks includes M/G data line driver cells, and

wherein each of the M/G data line driver cells drives one of the data lines.

10. The integrated circuit device as defined in claim 9 ,

the value “M/G” being a multiple of three when the display panel performs a color display,

the M/G data line driver cells including M/3G R data line driver cells, M/3G G data line driver cells and M/3G B data line driver cells, each of M/3G R data line driver cells driving a data line corresponding to an R pixel, each of M/3G G data line driver cells driving a data line corresponding to a G pixel, and each of M/3G B data line driver cells driving a data line corresponding to a B pixel, and

the M/G data line driver cells being arranged so that the R data line driver cells, the G data line driver cells, and the B data line driver cells are alternately disposed.

11. The integrated circuit device as defined in claim 9 ,

the value “N” being a multiple of three when the display panel performs a color display,

the M/G data line driver cells in a first group when dividing the first to Nth divided data line driver blocks into three groups including M/G R data line driver cells, each of which drives a data line corresponding to an R pixel,

the M/G data line driver cells in a second group including M/G G data line driver cells, each of which drives a data line corresponding to a G pixel,

the M/G data line driver cells in a third group including M/G B data line driver cells, each of which drives a data line corresponding to a B pixel, and

the M/G data line driver cells being arranged along the second direction.

12. The integrated circuit device as defined in claim 4 ,

each of the first to Nth divided data line driver blocks including first to Sth (S is an integer larger than one) subdivided data line drivers into which the divided data line driver is subdivided,

when a grayscale of a pixel corresponding to a data line is G bits, each of the first to Sth subdivided data line drivers includes M/(G×S) data line driver cells, each of which drives one of the data lines, and

the first to Sth subdivided data line drivers being disposed along the first direction.

13. The integrated circuit device as defined in claim 12 ,

an identical latch signal of the first to Nth latch signals being supplied to each of the first to Sth subdivided data line drivers.

14. The integrated circuit device as defined in claim 1 ,

the wordlines being formed parallel to a direction in which the data lines of the display panel extend.

15. An electronic instrument, comprising:

the integrated circuit device as defined in claim 1 ; and

a display panel.

16. The electronic instrument as defined in claim 15 ,

the integrated circuit device being mounted on a substrate which forms the display panel.

17. An integrated circuit device, comprising:

a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and

a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block,

the data line driver block including first to Nth (N is an integer larger than one) divided data line driver blocks, each of the first to Nth divided data line driver blocks driving a different data line group of the data line groups,

the wordline control circuit controlling (L×J=N) times of reading of data from the RAM block in one horizontal scan period of the display panel, by selecting an identical wordline L times (L is an integer larger than one) and J wordlines (J is an integer larger than one) as the identical wordline selected L times in the one horizontal scan period, and

the first to Nth divided data line driver blocks being disposed along a first direction in which the bitlines extend.

18. An integrated circuit device, comprising:

a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and

a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block,

the data line driver block including first to Nth (N is an integer larger than one) divided data line driver blocks, each of the first to Nth divided data line driver blocks driving a different data line group of the data line groups,

the wordline control circuit sequentially selecting N (N is an integer larger than one) different wordlines in one horizontal scan period of the display panel, and selects an identical wordline at least L times (L is an integer larger than one) in one vertical scan period of the display panel; and

the first to Nth divided data line driver blocks being disposed along a first direction in which the bitlines extend.

19. The integrated circuit device as defined in claim 18 ,

first to Nth latch signals being supplied to the first to Nth divided data line driver blocks, respectively, and

the first to Nth divided data line driver blocks latching data supplied from the RAM block based on the first to Nth latch signals.

20. The integrated circuit device as defined in claim 19 ,

when the wordlines are selected first time in the one horizontal scan period, the first latch signal is set to active so that data supplied from the RAM block in response to the first selection is latched by the first divided data line driver block, and, when the wordlines are selected Kth time (1≦K≦N; K is an integer), the Kth latch signal is set to active so that data supplied from the RAM block in response to the Kth selection is latched by the Kth divided data line driver block.

21. The integrated circuit device as defined in claim 19 ,

the RAM block including a sense amplifier circuit which outputs M-bit data (M is an integer larger than one) upon one wordline selection,

at least M×L memory cells being arranged in the RAM block along a second direction in which the wordlines extend, and

(M×L)-bit data being supplied to the sense amplifier circuit upon one wordline selection.

22. The integrated circuit device as defined in claim 21 ,

each of the first to Nth divided data line driver blocks drives one of the data line groups based on the M-bit data supplied from the RAM block, and

when a grayscale of a pixel corresponding to a data line is G bits, each of the first to Nth divided data line driver blocks includes M/G data line driver cells, and

each of the M/G data line driver cells drives one of the data lines.

23. The integrated circuit device as defined in claim 22 ,

the value “M/G” being a multiple of three when the display panel performs a color display,

the M/G data line driver cells including M/3G R data line driver cells, M/3G G data line driver cells and M/3G B data line driver cells, each of M/3G R data line driver cells driving a data line corresponding to an R pixel, each of M/3G G data line driver cells driving a data line corresponding to a G pixel, and each of M/3G B data line driver cells driving a data line corresponding to a B pixel, and

the M/G data line driver cells being arranged so that the R data line driver cells, the G data line driver cells, and the B data line driver cells are alternately disposed.

24. The integrated circuit device as defined in claim 22 ,

the value “N” being a multiple of three when the display panel performs a color display,

the M/G data line driver cells in a first group when dividing the first to Nth divided data line driver blocks into three groups including M/G R data line driver cells, each of which drives a data line corresponding to an R pixel,

the M/G data line driver cells in a second group including M/G G data line driver cells, each of which drives a data line corresponding to a G pixel,

the M/G data line driver cells in a third group including M/G B data line driver cells, each of which drives a data line corresponding to a B pixel, and

the M/G data line driver cells being arranged along the second direction.

25. The integrated circuit device as defined in claim 21 ,

each of the first to Nth divided data line driver blocks including first to Sth (S is an integer larger than one) subdivided data line drivers into which the divided data line driver is subdivided,

when a grayscale of a pixel corresponding to a data line is G bits, each of the first to Sth subdivided data line drivers includes M/(G×S) data line driver cells, each of which drives one of the data lines, and

the first to Sth subdivided data line drivers being disposed along the first direction.

26. The integrated circuit device as defined in claim 25 ,

an identical latch signal of the first to Nth latch signals being supplied to each of the first to Sth subdivided data line drivers.