IP Library Granted Patent US 7,259,031
Granted Patent B1
US 7,259,031 · App. 11/270,681 · Granted Aug 21, 2007

Integrated photonic-electronic circuits and systems

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Quick Facts
Patent No.
US 7,259,031
App. No.
11/270,681
Granted
Aug 21, 2007
Kind
B1
Abstract

Photonic interconnect reconfigurably couples integrated circuits such as microprocessor, memory or other logic components. Detector, modulator, broad-band coupler and waveguide elements provide transmit and receive capability on CMOS substrate. Computer-implemented design software and reusable component library automate photonic and circuit design and simulation for manufacturability.

Claims (40)

1. The integrated photonic-electronic design method comprising the steps of:

generating a design definition comprising an electronic circuit portion and a photonic interface integrated on a single chip, wherein the photonic interface comprises a coupler for coupling the circuit portion to one or more optical fibers and wherein one function of the photonic interface is to optically process light substantially in the plane of the chip; and

verifying the design definition by simulating one or more photonic-electronic models representing the design definition,

wherein:

the photonic interface comprises one or more receivers for receiving optical signals from one or more of the optical fibers.

2. The integrated photonic-electronic design method of claim 1 wherein:

the receiver comprises one or more broad-band couplers.

3. The integrated photonic-electronic design method of claim 1 wherein:

the receiver comprises one or more detectors.

4. The integrated photonic-electronic design method of claim 1 wherein:

the receiver further comprises one or more optical filters.

5. The integrated photonic-electronic design method of claim 4 wherein:

the optical filter is an optical demultiplexer, a waveguide based filter, an Arrayed Waveguide (AWG) demultiplexer, a ring resonator demultiplexer or an add/drop filter.

6. The integrated photonic-electronic design method comprising the steps of:

generating a design definition comprising an electronic circuit portion and a photonic interface integrated on a single chip, wherein the photonic interface comprises a coupler for coupling the circuit portion to one or more optical fibers and wherein one function of the photonic interface is to optically process light substantially in the plane of the chip; and

verifying the design definition by simulating one or more photonic-electronic models representing the design definition,

wherein:

the coupler comprises one or more transmitters for transmitting optical signals to one or more of the optical fibers.

7. The integrated photonic-electronic design method of claim 6 wherein:

the transmitter comprises one or more modulators.

8. The integrated photonic-electronic design method of claim 6 wherein:

the transmitter comprises one or more broad-band couplers.

9. The integrated photonic-electronic design method of claim 6 wherein:

the transmitter further comprises an optical filter.

10. The integrated photonic-electronic design method of claim 9 wherein:

the optical filter is an optical demultiplexer, a waveguide based filter, an Arrayed Waveguide (AWG) demultiplexer, a ring resonator demultiplexer, an optical multiplexer, an Arrayed Waveguide multiplexer, a ring resonator multiplexer or an add/drop filter.

11. The integrated photonic-electronic design method of claim 6 wherein:

the transmitter further comprises an optical power receiver for receiving optical power from an external optical power source.

12. The integrated photonic-electronic design method comprising the steps of:

generating a design definition comprising an electronic circuit portion and a photonic interface integrated on a single chip, wherein the photonic interface comprises a coupler for coupling the circuit portion to one or more optical fibers and wherein one function of the photonic interface is to optically process light substantially in the plane of the chip; and

verifying the design definition by simulating one or more photonic-electronic models representing the design definition,

wherein one or more of the optical fibers may be coupled to the top surface of the integrated photonic-electronic circuit surface.

13. The integrated photonic-electronic design method comprising the steps of:

generating a design definition comprising an electronic circuit portion and a photonic interface integrated on a single chip, wherein the photonic interface comprises a coupler for coupling the circuit portion to one or more optical fibers and wherein one function of the photonic interface is to optically process light substantially in the plane of the chip; and

verifying the design definition by simulating one or more photonic-electronic models representing the design definition,

wherein one or more of the optical fibers may be coupled to the backside surface of the integrated photonic-electronic circuit surface.

14. The integrated photonic-electronic design method comprising the steps of:

generating a design definition comprising an electronic circuit portion and a photonic interface integrated on a single chip, wherein the photonic interface comprises a coupler for coupling the circuit portion to one or more optical fibers and wherein one function of the photonic interface is to optically process light substantially in the plane of the chip; and

verifying the design definition by simulating one or more photonic-electronic models representing the design definition,

wherein one or more of the optical fibers may be coupled to the edge of the integrated photonic-electronic circuit surface.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNOR'S NAME PREVIOUSLY RECORDED AT REEL: 058979 FRAME: 0027. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 24, 2022
From: LUXTERA LLC
To: CISCO TECHNOLOGY, INC.
Reel/Frame 059496/0803 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2022
From: CISCO SYSTEMS, INC.
To: CISCO TECHNOLOGY, INC.
Reel/Frame 058979/0027 →
RELEASE OF SECURITY INTEREST Recorded Dec 24, 2020
From: SILICON VALLEY BANK
To: LUXTERA, LLC
Reel/Frame 054855/0838 →
CHANGE OF NAME Recorded Feb 6, 2020
From: LUXTERA, INC.
To: LUXTERA LLC
Reel/Frame 052019/0811 →
SECURITY INTEREST Recorded Mar 29, 2017
From: LUXTERA, INC.
To: SILICON VALLEY BANK
Reel/Frame 042109/0140 →
SECURITY AGREEMENT Recorded Jun 17, 2009
From: LUXTERA, INC.
To: SILICON VALLEY BANK
Reel/Frame 022835/0340 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2005
From: DICKINSON, ALEXANDER; GUNN III, LAWRENCE C.; NECHES, PHILIP M.; HUANG, ANDREW SHANE
To: LUXTERA, INC
Reel/Frame 017227/0994 →