IP Library Granted Patent US 8,350,600
Granted Patent B2
US 8,350,600 · App. 11/271,121 · Granted Jan 8, 2013

Glitchless clock multiplexer controlled by an asynchronous select signal

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Quick Facts
Patent No.
US 8,350,600
App. No.
11/271,121
Granted
Jan 8, 2013
Kind
B2
Abstract

A glitchless clock multiplexer controlled by an asynchronous select signal for use in GPS receivers is disclosed. A device in accordance with the present invention comprises a device for producing a clock signal, the clock signal being selected from a plurality of asynchronous frequency sources. A device in accordance with the present invention comprises a first frequency source, a second frequency source, a select signal, wherein the select signal is asynchronous with the first frequency source, and a multiplexer, which receives the first frequency source and the second frequency source, wherein the multiplexer selects as an output of the multiplexer one of the first frequency source and the second frequency source based on a value of the select signal, such that when the multiplexer switches between the first frequency source and the second frequency source, and between the second frequency source and the first frequency source, the transition is performed when the output of the multiplexer is at a logic low.

Claims (6)

1. A device for producing a clock signal, the clock signal being selected from a plurality of asynchronous frequency sources, comprising:

a first frequency source;

a second frequency source;

a select signal, wherein the select signal is asynchronous with both the first frequency source and the second frequency source; and

a multiplexer, which receives the first frequency source and the second frequency source, wherein the multiplexer selects as an output of the multiplexer one of the first frequency source and the second frequency source based on a value of the select signal, such that when the multiplexer switches between the first frequency source and the second frequency source, and between the second frequency source and the first frequency source, the transition is performed when the output of the multiplexer is at a logic low, wherein the first frequency source is powered on prior to switching to the second frequency source and powered down after switching to the second frequency source wherein the first frequency source is a Voltage Controlled Oscillator (VCO); the second frequency source is a crystal oscillator; the select signal is a binary signal; and the device is used in a Global Positioning System (GPS) receiver.

2. The device of claim 1 , wherein a state of the binary select signal is chosen to minimize power consumption of the GPS receiver when the GPS receiver is in a low power mode.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2012
From: QUALCOMM ATHEROS TECHNOLOGY LTD.
To: QUALCOMM INCORPORATED
Reel/Frame 029421/0993 →
CHANGE OF NAME Recorded Aug 22, 2011
From: ATHEROS TECHNOLOGY LTD.
To: QUALCOMM ATHEROS TECHNOLOGY LTD.
Reel/Frame 026786/0727 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 6, 2008
From: U-NAV MICROELECTRONICS CORPORATION
To: ATHEROS TECHNOLOGY LTD.
Reel/Frame 020609/0116 →
RELEASE OF SECURITY INTEREST IN PATENTS Recorded Jan 4, 2008
From: BROADCOM CORPORATION
To: U-NAV MICROELECTRONICS CORPORATION
Reel/Frame 020317/0511 →
GRANT OF PATENT SECURITY INTEREST Recorded Feb 16, 2007
From: U-NAV MICROELECTRONICS CORPORATION
To: BROADCOM CORPORATION
Reel/Frame 018898/0492 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2005
From: LEON, CHRISTOPHER R.
To: U-NAV MICROELECTRONICS CORPORATION
Reel/Frame 017236/0992 →