Method to eliminate PLL lock-up during power up for high frequency synthesizer
A method and apparatus to eliminate PLL lock-up during power-up for a VCO. A method in accordance with the present invention comprises coupling a divider to a Voltage Controlled Oscillator (VCO) to create the feedback loop, and driving the divider with a signal, wherein the signal from the VCO is at high frequency upon power up.
1 . A method for preventing lock-up in a feedback loop, comprising:
coupling a divider to a Voltage Controlled Oscillator (VCO) to create the feedback loop; and
driving the divider with a signal, wherein an output of the VCO is at high frequency when a control signal is at a low voltage.
2 . The method of claim 1 , wherein the output of the VCO is at a high amplitude when the control signal is at a low voltage.
3 . The method of claim 2 , wherein the feedback loop is a phase-locked loop.
4 . The method of claim 3 , wherein the divider is operated in a preferred region of operation upon power up.
5 . The method of claim 4 , wherein the feedback loop is used in a GPS receiver.
6 . A Global Positioning System (GPS) Receiver, comprising:
a radio frequency section;
a baseband section; and
a feedback loop controlled frequency source, coupled to at least one of the baseband section and the radio frequency section, wherein the frequency source is driven to a high frequency at power-up of the GPS receiver.
7 . The GPS receiver of claim 6 , wherein the frequency source is a Voltage Controlled Oscillator (VCO).
8 . The GPS receiver of claim 7 , wherein the feedback loop is a phase-locked loop (PLL).
9 . The GPS receiver of claim 8 , further comprising a divider, coupled to the frequency source within the phase-locked loop.
10 . The GPS receiver of claim 9 , wherein the divider is operated in a preferred region of operation at power up.