Two-bit offset cancelling A/D converter with improved common mode rejection and threshold sensitivity
View Patent ↗A two-bit offset canceling A/D converter with improved common mode rejection and threshold sensitivity for use in GPS receivers. A device in accordance with the present invention comprises a level shifter, the level shifter receiving a positive signal and a negative signal, the level shifter shifting the positive signal and the negative signal such that a difference between the positive signal and the negative signal is larger than a threshold value, and a comparator, coupled to the level shifter, the comparator providing as outputs of the comparators a sign bit and two magnitude bits wherein the comparator comprises a plurality of switched capacitor amplifiers.
1. A device for converting analog signals to digital signals, comprising:
a level shifter, the level shifter receiving a positive signal and a negative signal, the level shifter shifting the positive signal and the negative signal such that a difference between the positive signal and the negative signal is larger than a threshold value; and
a comparator, coupled to the level shifter, the comparator providing as outputs of the comparator at least a sign bit and two magnitude bits, wherein the comparator comprises a plurality of switched capacitor amplifiers.
2. The device of claim 1 , wherein the difference is approximately twice the threshold value.
3. The device of claim 2 , wherein the level shifter creates the difference using a voltage drop across a resistor.
4. The device of claim 3 , wherein the positive signal and the negative signal are applied to a control input of first transistor and a control input of a second transistor in a respective fashion.
5. The device of claim 4 , wherein the device is used in a GPS receiver.
6. The device of claim 5 , wherein the device is used in a baseband section of the GPS receiver.
7. The device of claim 6 , wherein the positive signal is compared directly to the threshold voltage and the negative signal is compared directly to the threshold voltage, such that noise on the threshold voltage is canceled out.
8. A Global Positioning System (GPS) Receiver, comprising:
a radio frequency (RF) section;
a baseband section; and
an analog-to-digital converter, receiving a positive signal and a negative signal, the analog-to-digital converter comprising a comparator, the comparator providing as outputs of the comparator a first bit, a second bit, and an offset between the positive signal and the negative signal.
9. The GPS receiver of claim 8 , further comprising a level shifter, coupled to the comparator, the level shifter receiving the positive signal and the negative signal and shifting the positive signal and the negative signal such that a difference between the positive signal and the negative signal is larger than a threshold value; and forwarding the shifted positive signal and the shifted negative signal to the comparator.
10. The GPS receiver of claim 8 , wherein the positive signal and the negative signal are applied to a control input of first transistor and a control input of a second transistor in a respective fashion.
11. The GPS receiver of claim 10 , wherein the first transistor and the second transistor are Metal-Oxide-Semiconductor (MOS) transistors.
12. The GPS receiver of claim 11 , wherein the analog-to-digital converter is resident in the baseband section.
13. The GPS receiver of claim 12 , wherein the comparator comprises a plurality of switched capacitor amplifiers.
14. The GPS receiver of claim 13 , wherein the difference is approximately twice the threshold value.