AM demodulator
View Patent ↗An amplitude modulation receiver including an antenna for receiving a signal and an input filter connected to the antenna. A variable gain amplifier is connected to the input filter and is responsive to a gain control signal. An A/D converter is connected to the variable gain amplifier and is responsive to a sampling signal and provides a sampled digital signal. A D/A converter receives a demodulated signal and provides an analog output signal. A controller receives and demodulates the sampled digital signal from the A/D converter, generates the gain control signal for the variable gain amplifier, generates the sampling signal for the A/D converter, and provides the demodulated signal to the D/A converter. The demodulation and generation of the gain control signal and the sampling signal are performed in software.
1. A demodulator for an amplitude modulation receiver, which comprises:
an input filter for filtering an input signal;
a decimator and integrator demodulator for demodulating the filtered input signal; and
an output filter for filtering the demodulated signal, wherein:
the filtered input signal s(t) is segmented by a windowing function g(t−mT c ), where T c is a cycle time period;
the segments of the filtered input signal s(t) are multiplied by the carrier frequency w k , which produces demodulated segments d(t);
the demodulated segments d(t) are segmented by a windowing function g(t−lT c ),
the segmented demodulated signals d(t) are integrated over the cycle period T c , every period; and
the integrated demodulated segments are summed and filtered by the output filter, which produces the modulation function φ k [nT c ].
2. The demodulator according to claim 1 , wherein coefficients of the filters for each carrier frequency are stored in the demodulator.
3. The demodulator according to claim 1 , wherein the input and output filters filter the input signal and the integrated demodulated signal respectively to band pass about the carrier frequency.
4. The demodulator according to claim 1 , wherein the demodulator is a multi-thread processor implementing the functions of the input filtering, decimation, integration and output filtering in parallel.
5. The demodulator according to claim 1 , wherein the decimator and integrator demodulator decimates the integrated demodulated signal through a predetermined decimation ratio before being forwarded to the output filter.
6. The demodulator according to claim 5 , wherein the predetermined decimation ratio is a 1:8 ratio.
7. The demodulator according to claim 5 , wherein the predetermined decimation ratio is a 1:16 ratio.
8. The demodulator according to claim 5 , wherein the predetermined decimation ratio is a 1:32 ratio.
9. The demodulator according to claim 1 , further comprising:
a multiplier positioned before the decimator and integrator demodulator.
10. The demodulator according to claim 9 , wherein the demodulator and the input filter are tuned to the carrier frequency of the input signal and the output filter is tuned to a decimated carrier frequency.