System and method for aligning data in a network environment

1. An apparatus for aligning data, comprising:

a first buffer operable to receive a first data signal, a first write address signal, and a first clock signal, the first buffer operable to store a particular byte of the first data signal in a particular location of the first buffer in response to the first write address signal and the first clock signal, the first buffer operable to receive a recovered clock signal, the first buffer operable to transmit a stored first data signal in response to the recovered clock signal, the recovered clock signal operable to control a read address of the first buffer in transmitting the first data signal from the first buffer;

an output timer operable to receive the recovered clock signal and a recovered reference signal, the output timer operable to control the read address of the first buffer to place the first data signal in alignment with a second data signal.

2. The apparatus of claim 1 , further comprising:

a first phase aligner input timer operable to receive the first clock signal and a first frame signal, the first phase aligner input timer operable to generate the first write address signal in response to the first clock signal and the first frame signal, the first write address signal operable to control the write address of the first buffer in storing the first data signal.

3. The apparatus of claim 2 , further comprising:

a first framer state machine operable to filter out momentary disturbances or bit errors in the first frame signal.

4. The apparatus of claim 1 , further comprising:

a selector operable to receive the first data signal and the second data signal, the selector operable to select one of the first and second data signals for output.

5. The apparatus of claim 4 , wherein the selector is operable to select one of the first and second data signals on a frame by frame basis.

6. The apparatus of claim 1 , further comprising:

an offset register operable to establish an initial state for the output timer.

7. The apparatus of claim 6 , wherein the offset register is loaded with a value according to a size of the first buffer.

8. The apparatus of claim 1 , wherein a specific byte of the first data signal is stored at a unique location of the first buffer.

9. An apparatus for aligning data, comprising:

a first buffer operable to receive a first data signal and a first clock signal, the first buffer operable to store the first data signal in response to the first clock signal, the first clock signal operable to control a write address of the first buffer in storing the first data signal, the first buffer operable to receive a recovered clock signal, the first buffer operable to transmit a stored first data signal in response to the recovered clock signal, the recovered clock signal operable to control a read address of the first buffer in transmitting the first data signal from the first buffer;

an output timer operable to receive the recovered clock signal and a recovered reference signal, the output timer operable to control the read address of the first buffer to place the first data signal in alignment with a second data signal;

a timer decode unit operable to generate an expected framing pattern associated with the first data signal;

a frame alignment checker operable to receive the first data signal transmitted from the first buffer, the frame alignment signal operable to compare the first data signal to the expected framing pattern, the frame alignment checker operable to locate a first byte of a frame in the first data signal.

10. The apparatus of claim 9 , wherein the frame alignment checker is operable to generate a slip signal in response to the first data signal not matching the expected framing pattern, the slip signal operable to adjust the read address of the first buffer.

11. A method for aligning data, comprising:

receiving a first data signal, a first write address signal, and a first clock signal;

storing a particular byte of the first data signal in a particular location in response to the first write address and the first clock signal;

receiving a recovered clock signal;

transmitting the stored first data signal in response to the recovered clock signal;

controlling a read address with the recovered clock signal in transmitting the first data signal;

receiving a recovered reference signal;

adjusting the read address to place the first data signal in alignment with a second data signal.

12. The method of claim 11 , further comprising:

receiving a first frame signal;

generating the first write address signal in response to the first clock signal and the first frame signal;

controlling the write address with the write address signal in storing the first data signal.

13. A method for aligning data, comprising:

receiving a first data signal and a first clock signal;

storing the first data signal in response to the first clock signal;

controlling a write address with the first clock signal in storing the first data signal;

receiving a recovered clock signal;

transmitting the stored first data signal in response to the recovered clock signal;

controlling a read address with the recovered clock signal in transmitting the first data signal;

receiving a recovered reference signal;

adjusting the read address to place the first data signal in alignment with a second data signal;

generating an expected framing pattern associated with the first data signal;

comparing the transmitted first data signal to the expected framing pattern;

locating a first byte of a frame in the transmitted first data signal.

14. The method of claim 13 , further comprising:

generating a slip signal in response to the transmitted first data signal not matching the expected framing pattern;

adjusting the read address with the slip signal.