IP Library Granted Patent US 7,199,745
Granted Patent B2
US 7,199,745 · App. 11/273,025 · Granted Apr 3, 2007

Successive approximation A/D converter provided with a sample-hold amplifier

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Quick Facts
Patent No.
US 7,199,745
App. No.
11/273,025
Granted
Apr 3, 2007
Kind
B2
Abstract

A successive approximation A/D converter includes a sample-hold amplifier circuit configured to sample and hold an input analog voltage to produce an internal analog voltage proportional to the input analog voltage with a voltage gain being smaller than 1, a switched capacitor D/A converter coupled to the sample-hold amplifier circuit and including a plurality of capacitors for storing electric charge responsive to the internal analog voltage, the switched capacitor D/A converter configured to switch couplings of the capacitors in response to a control signal to produce a comparison analog voltage responsive to the internal analog voltage and the control signal, a comparator coupled to the switched capacitor D/A converter to produce a comparison result signal responsive to the comparison analog voltage, and a control circuit coupled to the comparator to supply the control signal responsive to the comparison result signal to the switched capacitor D/A converter.

Claims (37)

1. A successive approximation A/D converter, comprising:

a sample-hold amplifier circuit configured to sample and hold an input analog voltage to produce at an output node an internal analog voltage proportional to the input analog voltage with a voltage gain being smaller than 1;

a switched capacitor D/A converter coupled to the output node of said sample-hold amplifier circuit and including a plurality of capacitors for storing electric charge responsive to the internal analog voltage, each of the plurality of capacitors having one end thereof connected to the output node of the sample-hold amplifier circuit at a time of storing the electric charge so that said one end receives the internal analog voltage having the voltage gain smaller than 1, and said switched capacitor D/A converter configured to switch couplings of the capacitors in response to a control signal to produce at an output node a comparison analog voltage responsive to the internal analog voltage and the control signal;

a comparator coupled to the output node of said switched capacitor D/A converter to produce at an output node a comparison result signal responsive to the comparison analog voltage; and

a control circuit coupled to the output node of said comparator to supply the control signal responsive to the comparison result signal to said switched capacitor D/A converter.

2. A successive approximation A/D converter, comprising:

a sample-hold amplifier circuit configured to sample and hold an input analog voltage to produce at an output node an internal analog voltage proportional to the input analog voltage with a voltage gain being smaller than 1;

a switched capacitor D/A converter coupled to the output node of said sample-hold amplifier circuit and including a plurality of capacitors for storing electric charge responsive to the internal analog voltage, said switched capacitor D/A converter configured to switch couplings of the capacitors in response to a control signal to produce at an output node a comparison analog voltage responsive to the internal analog voltage and the control signal;

a comparator coupled to the output node of said switched capacitor D/A converter to produce at an output node a comparison result signal responsive to the comparison analog voltage; and

a control circuit coupled to the output node of said comparator to supply the control signal responsive to the comparison result signal to said switched capacitor D/A converter,

wherein the capacitors of said switched capacitor D/A converter include:

one or more first capacitors selectively coupled to either one of two reference potentials in response to the control signal; and

one or more second capacitors coupled to a predetermined one of the two reference potentials regardless of the control signal,

wherein the switched capacitor D/A converter is configured to adjust the comparison analog voltage by use of said second capacitors so as to compensate for the voltage gain of said sample-hold amplifier circuit being smaller than 1.

3. The successive approximation A/D converter as claimed in claim 2 , wherein said switched capacitor D/A converter is configured to adjust the comparison analog voltage by use of said second capacitors such that all of said first capacitors are coupled to a same one of the two reference potential when the input analog voltage is equal to a difference between the two reference potentials.

4. A successive approximation A/D converter, comprising:

a sample-hold amplifier circuit configured to sample and hold an input analog voltage to produce at an output node an internal analog voltage proportional to the input analog voltage with a voltage gain being smaller than 1;

a switched capacitor D/A converter coupled to the output node of said sample-hold amplifier circuit and including plurality of capacitors for storing electric charge responsive to the internal analog voltage, said switched capacitor D/A converter configured to switch couplings of the capacitors in response to a control signal to produce at an output node a comparison analog voltage responsive to the internal analog voltage and the control signal;

a comparator coupled to the output node of said switched capacitor D/A converter to produce at an output node a comparison result signal responsive to the comparison analog voltage; and

a control circuit coupled to the output node of said comparator to supply the control signal responsive to the comparison result signal to said switched capacitor D/A converter,

wherein said sample-hold amplifier circuit is a switched capacitor sample-hold amplifier that includes:

an amplifier circuit;

a first capacitor coupled to an input node side of said amplifier circuit; and

a second capacitor coupled to an output node side of said amplifier circuit,

wherein a capacitance of said second capacitor is larger than a capacitance of said first capacitor.

5. The successive approximation A/D converter as claimed in claim 4 , wherein said amplifier circuit includes:

a first amplifier circuit having an input node coupled to the input node side and an output node fed back to the input node side; and

a second amplifier circuit having an input node coupled to the output node of said first amplifier circuit to produce the internal analog voltage at an output node.

6. A successive approximation A/D converter, comprising:

a sample-hold amplifier circuit configured to sample and hold an input analog voltage to produce at an output node an internal analog voltage proportional to the input analog voltage with a voltage gain being smaller than 1;

a switched capacitor D/A converter coupled to the output node of said sample-hold amplifier circuit and including a plurality of capacitors for storing electric charge responsive to the internal analog voltage, said switched capacitor D/A converter configured to switch couplings of the capacitors in response to a control signal to produce at an output node a comparison analog voltage responsive to the internal analog voltage and the control signal;

a comparator coupled to the output node of said switched capacitor D/A converter to produce at an output node a comparison result signal responsive to the comparison analog voltage;

a control circuit coupled to the output node of said comparator to supply the control signal responsive to the comparison result signal to said switched capacitor D/A converter; and

a resistor D/A converter having an output node thereof coupled to one of the capacitors that has a smallest capacitance.

7. The successive approximation A/D converter as claimed in claim 6 , wherein said resistor D/A converter includes:

a plurality of resistors connected in series between two reference potentials; and

a selector configured to select one of a plurality of divided potentials generated by said plurality of resistors.

Assignments (10)
MERGER Recorded Nov 14, 2025
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 073571/0456 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036038/0620 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
CHANGE OF NAME Recorded Jul 22, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024982/0245 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021998/0645 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2005
From: TACHIBANA, SUGURU; MITSUDA, KAZUHIRO; KATO, TATSUO
To: FUJITSU LIMITED
Reel/Frame 017231/0212 →