Structure and manufacturing method of semiconductor memory device
View Patent ↗A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.
1. A method for manufacturing a semiconductor memory device having a cross point structure, comprising:
depositing on a semiconductor substrate a first insulating material and a lower electrode material for lower electrodes;
patterning and planarizing the first insulating material and/or the lower electrode material to configure the lower electrodes such that surfaces of the lower electrodes and the first insulating material are substantially coplanar;
depositing a memory material of a perovskite material on the surfaces of the lower electrodes and the first insulating material;
depositing an upper electrode material for upper electrodes on the memory material;
patterning the memory material and the upper electrode material with a use of an upper electrode masking to configure the upper electrodes; and
depositing a second insulating material on the upper electrodes,
wherein the lower electrodes extend in a direction,
wherein the upper electrodes extend in a direction substantially perpendicular to the direction of the lower electrodes,
wherein the patterned memory material extend along corresponding to the upper electrodes, and
wherein each lower electrode spans multiple upper electrodes such that each lower electrode extends beyond a cell region of a memory cell, which is an area defined by a cross-section between the lower electrode and any upper electrode spanned by the lower electrode.
2. The method for manufacturing a semiconductor memory device according to claim 1 , wherein the step of depositing on the semiconductor substrate the first insulating material and the lower electrode material and the step of patterning and planarizing the first insulating material and/or the lower electrode material comprise:
depositing in succession on the semiconductor substrate the lower electrode material for the lower electrodes and a surface protecting layer for protecting surfaces of the lower electrodes; and
patterning the lower electrode material and the surface protecting layer with a use of a lower electrode masking to configure the lower electrodes,
depositing the first insulating material on the lower electrodes and the surface protecting layer;
planarizing the first insulating material to expose the surface protecting layer; and
removing the surface protecting layer.
3. The method for manufacturing the semiconductor memory device according to claim 2 , wherein the act of patterning with the lower electrode masking includes a process of dry etching.
4. The method for manufacturing the semiconductor memory device according to claim 2 , wherein the act of planarizing includes a process of chemical and mechanical polishing.
5. The method for manufacturing the semiconductor memory device according to claim 2 , wherein the act of patterning with the upper electrode masking includes a process of dry etching.
6. The method for manufacturing the semiconductor memory device according to claim 2 , further comprising:
patterning a memory circuit prior to the act of depositing the perovskite material.
7. The method for manufacturing the semiconductor memory device according to claim 2 , wherein a memory cell of the memory device occupies an area substantially equal to 4F 2 , where F is a minimum width of the patterning process.
8. The method for manufacturing the semiconductor memory device according to claim 2 , wherein the memory material does not extend along the lower electrodes.
9. The method for manufacturing a semiconductor memory device according to claim 1 , wherein the step of depositing on the semiconductor substrate the first insulating material and the lower electrode material and the step of patterning and planarizing the first insulating material and/or the lower electrode material comprise:
depositing the lower electrode material on the substrate;
patterning the lower electrode material with a use of a lower electrode masking to configure the lower electrodes;
depositing a first insulating material on the lower electrodes and on the substrate; and
planarizing the first insulating material to expose the surfaces of the lower electrodes.
10. The method for manufacturing the semiconductor memory device according to claim 9 , wherein the act of patterning with the lower electrode masking includes a process of dry etching.
11. The method for manufacturing the semiconductor memory device according to claim 9 , wherein the act of planarizing includes a process of chemical and mechanical polishing.
12. The method for manufacturing the semiconductor memory device according to claim 9 , wherein the act of patterning with the upper electrode masking includes a process of dry etching.
13. The method for manufacturing the semiconductor memory device according to claim 9 , further comprising:
patterning a memory circuit prior to the act of depositing the perovskite material.
14. The method for manufacturing the semiconductor memory device according to claim 9 , wherein a memory cell of the memory device occupies an area substantially equal to 4F 2 , where F is a minimum width of the patterning process.
15. The method for manufacturing the semiconductor memory device according to claim 9 , wherein the memory material does not extend along the lower electrodes.
16. The method for manufacturing a semiconductor memory device according to claim 1 , wherein the step of depositing on the semiconductor substrate the first insulating material and the lower electrode material and the step of patterning and planarizing the first insulating material and/or the lower electrode material comprise:
depositing on the semiconductor substrate the first insulating material;
patterning the first insulating material with a use of a lower electrode masking;
depositing the lower electrode material for the lower electrodes on the patterned first insulating material; and
planarizing the lower electrode material to expose the surface of the first insulating material and configure the lower electrodes.
17. The method for manufacturing the semiconductor memory device according to claim 16 , wherein the act of patterning with the lower electrode masking includes a process of dry etching.
18. The method for manufacturing the semiconductor memory device according to claim 16 , wherein the act of planarizing includes a process of chemical and mechanical polishing.
19. The method for manufacturing the semiconductor memory device according to claim 16 , wherein the act of patterning with the upper electrode masking includes a process of dry etching.
20. The method for manufacturing the semiconductor memory device according to claim 16 , further comprising:
patterning a memory circuit prior to the act of depositing the perovskite material.
21. The method for manufacturing the semiconductor memory device according to claim 16 , wherein a memory cell of the memory device occupies an area substantially equal to 4F 2 , where F is a minimum width of the patterning process.
22. The method for manufacturing the semiconductor memory device according to claim 16 , wherein the memory material does not extend along the lower electrodes.
23. The method for manufacturing the semiconductor memory device according to claim 1 , wherein the perovskite material is in direct contact with both the upper and lower electrodes.