IP Library Granted Patent US 7,952,442
Granted Patent B2
US 7,952,442 · App. 11/274,825 · Granted May 31, 2011

Integrated circuit package having inductance loop formed from same-pin-to-same-bonding-pad structure

Assignee: GCT Semiconductor, Inc.
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Quick Facts
Patent No.
US 7,952,442
App. No.
11/274,825
Granted
May 31, 2011
Kind
B2
Abstract

An integrated circuit package includes an inductance loop formed from a connection of bonding wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a bonding pad on the integrated circuit chip to an I/O pin of the package and a second wire which connects the same bonding pad to the same pin. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization.

Claims (15)

1. An oscillator circuit, comprising:

an active oscillator having two output nodes;

an inductor loop coupled to the output nodes; and

at least one capacitive circuit coupled to one of the output nodes, said capacitive circuit including a capacitor, a resistor, and a first switch, wherein said resistor provides a bias voltage to the capacitor when the first switch is open and wherein said first switch couples and decouples the capacitor to the output nodes of the active oscillator, and wherein the active oscillator and capacitive circuit are included in a semiconductor package which includes an integrated circuit chip, said inductor loop including:

a first conductor connecting a bonding pad on the chip to an input/output pin of a semiconductor package; and

a second conductor connecting the bonding pad on the chip to the input/output pin of the package.

2. The oscillator circuit of claim 1 , wherein the first conductor and the second conductor are bonding wires.

3. The oscillator circuit of claim 1 , wherein the inductor loop includes at least a third conductor connecting the bonding pad on the chip to the input/output pin of the package.

4. An oscillator circuit, comprising:

an active oscillator having two output nodes;

an inductor loop coupled to the output nodes; and

at least one capacitive circuit coupled to one of the output nodes, said capacitive circuit including a capacitor, a resistor, and a first switch, wherein said resistor provides a bias voltage to the capacitor when the first switch is open and wherein said first switch couples and decouples the capacitor to the output nodes of the active oscillator, and wherein the active oscillator and capacitive circuit are included in a semiconductor package which includes an integrated circuit chip, said inductor loop including:

(a) a first sub-loop which includes a first conductor connecting a bonding pad on the chip to an input/output pin of the package and second conductor connecting the bonding pad on the chip to the input/output pin of the package; and

(b) a second sub-loop which includes one of the first conductor and the second conductor and a third conductor connecting the bonding pad on the chip to the input/output pin of the package.

5. The oscillator circuit of claim 4 , wherein the first conductor and the second conductor are bonding wires.

Assignments (2)
RELEASE OF SECURITY INTEREST Recorded Dec 17, 2015
From: COMERICA BANK
To: GCT SEMICONDUCTOR, INC.
Reel/Frame 037327/0085 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Mar 29, 2013
From: GCT SEMICONDUCTOR, INC.
To: COMERICA BANK
Reel/Frame 030112/0447 →
Continuity (3)
Continuation 10927014 · Aug 27, 2004
Provisional Application 60498353 · Aug 28, 2003
Related Publication 20060081973A1 · Apr 20, 2006