Thin film transistor (TFT) array panel with TFTs having varying leakage currents
View Patent ↗A thin film transistor (TFT) array panel is provided, which includes a substrate, a plurality of gate lines including gate electrodes, a plurality of data lines intersecting the gate lines; a plurality of TFTs having semiconductors, connected to the gate lines and the data lines, and a plurality of pixel electrodes connected to the TFTs, wherein the TFTs have varying leakage currents, and the TFTs are randomly distributed.
1. A thin film transistor (TFT) array panel comprising:
a substrate;
a plurality of gate lines including gate electrodes;
a plurality of data lines intersecting the gate lines;
a plurality of TFTs having semiconductor islands connected to the gate lines and the data lines; and
a plurality of pixel electrodes connected to the TFTs,
wherein the gate electrodes are slanted with respect to the gate lines in a plane view and overlap the semiconductor islands in varying slant directions in the plane view to make the TFTs have varying leakage currents, and the TFTs are randomly distributed.
2. The TFT array panel of claim 1 , wherein the semiconductor islands and the gate electrodes overlap each other with varying overlapping areas to form the varying leakage currents.
3. The TFT array panel of claim 1 , further comprising:
a blocking layer formed between the substrate and the semiconductor islands.
4. The TFT array panel of claim 1 , further comprising:
a passivation layer formed between the pixel electrodes and the gate and data lines.
5. The TFT array panel of claim 1 , further comprising:
an interlayer insulating layer formed between the gate lines and the data lines.
6. The TFT array panel of claim 1 , further comprising:
a partition formed on the pixel electrodes, and
a plurality of light emitting members formed on the pixel electrodes and disposed in openings defined by the partition.
7. A thin film transistor (TFT) array panel comprising:
a substrate;
a plurality of gate lines including gate electrodes;
a plurality of data lines intersecting the gate lines;
a plurality of TFTs connected to the gate lines and the data lines; and
a plurality of pixel electrodes connected to the TFTs,
wherein at least two of the gate electrodes of a gate line are slanted in varying slant directions, and wherein each of the slanted gate electrodes is slanted with respect to an extending direction of part of the gate line from which the slanted gate electrode protrudes in a plane view.
8. The TFT array panel of claim 7 , further comprising:
a passivation layer formed between the pixel electrodes and the gate and data lines.
9. The TFT array panel of claim 7 , further comprising:
an interlayer insulating layer formed between the gate lines and the data lines.
10. The TFT array panel of claim 7 , further comprising:
a partition formed on the pixel electrodes, and
a plurality of light emitting members formed on the pixel electrodes and disposed in openings defined by the partition.
11. The TFT array panel of claim 7 , wherein the TFT comprises a semiconductor island, and the gate electrode overlaps a respective semiconductor island.
12. The TFT array panel of claim 11 , further comprising:
a blocking layer formed between the substrate and the semiconductor islands.