Memory cell system using silicon-rich nitride
View Patent ↗A memory cell system including providing a substrate, forming a charge-storing stack having silicon-rich nitride on the substrate, and forming a gate on the charge-storing stack.
1. A method of producing a memory cell system, said method comprising:
providing a substrate;
forming a charge-storing stack on said substrate, wherein said forming said charge-storing stack comprises:
forming a first insulating layer,
forming a tunneling layer directly on said first insulating layer,
forming a first silicon-rich nitride charge-storing layer over said tunneling layer,
forming at least a second silicon-rich nitride charge-storing layer directly on said first silicon-rich nitride charge storing layer, and
forming a second insulating layer directly over said at least second silicon-rich nitride charge-storing layer; and
forming a gate on said charge-storing stack.
2. The method of claim 1 , wherein said forming said charge-storing stack further comprises forming two or more charge-storing locations.
3. The method of claim 1 , wherein each of said first and said at least second silicon-rich nitride charge-storing layers has a different silicon richness.
4. The method of claim 1 further comprising forming a source and a drain in said substrate.
5. A memory cell system comprising:
a substrate;
a charge-storing stack on said substrate, wherein said charge-storing stack comprises:
a first insulating layer,
a tunneling layer directly on said first insulating layer,
a first silicon-rich nitride charge-storing layer over said tunneling layer,
at least a second silicon-rich, nitride charge-storing layer directly on said first silicon-rich nitride charge-storing layer, and
a second insulating layer formed directly over said at least second silicon-rich nitride charge-storing layer; and
a gate on said charge-storing stack.
6. The system of claim 5 , wherein said charge-storing stack further comprises two or more charge-storing locations.
7. The system of claim 5 , wherein each of said first and said at least second silicon-rich nitride charge-storing layers has a different silicon richness.
8. The system of claim 5 , wherein said substrate further comprises a source and a drain.
9. A method of producing a memory cell system, said method comprising:
providing a substrate having at least one bitline;
forming a first insulating layer on said substrate;
forming a plurality of silicon-rich nitride charge-storing regions over said first insulating layer, wherein at least one of said plurality of silicon-rich nitride charge-storing regions is above and generally aligned with said at least one bitline, and each of said plurality of silicon-rich nitride charge-storing regions are laterally spaced apart from one another by a respective silicon nitride insulating region formed on said first insulating layer;
forming a second insulating layer on said plurality of silicon-rich nitride charge-storing layer and said respective silicon nitride insulating region; and
forming a gate on said second insulating layer.
10. The method of claim 9 further comprising forming a blocking layer between said second insulating layer and said gate.
11. The method of claim 10 , wherein said blocking layer comprises a high-K dielectric.
12. The method of claim 10 , wherein said blocking layer comprises a high-K alumina (Al 2 O 3 ).
13. The method of claim 9 , wherein said forming said plurality of silicon-rich nitride charge-storing regions further comprises forming two or more charge-storing locations for each of said at least one bitline.
14. The method of claim 9 further comprising forming a source and a drain in said substrate.
15. A memory cell system comprising:
a substrate having at least one bitline;
a first insulating layer on said substrate;
a plurality of silicon-rich nitride charge-storing regions over said first insulating layer, wherein at least one of said plurality of silicon-rich nitride charge-storing regions is above and generally aligned with said at least one bitline, and each of said plurality of silicon-rich nitride charge-storing regions are laterally spaced apart from one another by a respective silicon nitride insulating region formed on said first insulating layer;
a second insulating layer on said plurality of silicon-rich nitride charge-storing regions and said respective silicon nitride insulating region; and
a gate on said second insulating layer.
16. The system of claim 15 further comprising a blocking layer between said second insulating layer and said gate.
17. The system of claim 16 , wherein said blocking layer comprises a high-K dielectric.
18. The system of claim 16 , wherein said blocking layer comprises a high-K alumina (Al 2 O 3 ).
19. The system of claim 15 , wherein said plurality of silicon-rich nitride charge-storing regions further comprises two or more charge-storing locations for each of said at least one bitline.
20. The system of claim 15 , wherein said substrate further comprises a source and a drain.