IP Library Granted Patent US 7,436,356
Granted Patent B2
US 7,436,356 · App. 11/277,363 · Granted Oct 14, 2008

Method of cross-correlation and continuous wave interference suppression for GPS signal and associated GPS receiver

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Quick Facts
Patent No.
US 7,436,356
App. No.
11/277,363
Granted
Oct 14, 2008
Kind
B2
Abstract

A method for processing weak indoor signals in presence of cross-correlation or continuous wave interference and associated GPS receiver are provided. The method comprises providing a two-dimensional delay-Doppler accumulated power pattern having a plurality of accumulated powers corresponding to frequency and time; for a predetermined frequency, determining an average value of accumulated powers of the two-dimensional delay-Doppler accumulated power pattern over a plurality of times; and subtracting the average value from the accumulated powers used in determining the average at the frequency over the plurality of times to generate a delay-Doppler accumulated power pattern with suppressed interference effect.

Claims (19)

1. A method for a global positioning system (GPS) receiver to suppress an to suppress an interference effect on a two-dimensional delay-Doppler accumulated power pattern, the method comprising:

providing a two-dimensional delay-Doppler accumulated power pattern comprising a plurality of accumulated powers corresponding to frequency and time;

for a predetermined frequency, determining an average value of accumulated powers of the two-dimensional delay-Doppler accumulated power pattern over a plurality of time points by excluding accumulated power value at a maximum time point and two time points adjacent to the maximum; and

subtracting the average value from the accumulated powers to generate a delay-Doppler accumulated power pattern with suppressed interference effect.

2. The method of claim 1 further comprising repeating the determining and subtracting steps for a plurality of frequencies to generate a two-dimensional delay-Doppler accumulated power pattern with suppressed interference effect.

3. The method of claim 1 , wherein the average value is obtained by calculating an arithmetic means, a medium, or a mode.

4. The method of claim 1 , wherein the average value is obtained by referencing a lookup table.

5. The method of claim 1 , wherein the predetermined frequency is a Doppler bin of the two-dimensional delay-Doppler accumulated power pattern and each time point is associated with a code bin of the two-dimensional delay-Doppler accumulated power pattern.

6. A global positioning system (GPS) receiver comprising:

an antenna;

a radio-frequency front-end coupled to the antenna;

digital signal processing circuitry coupled to the radio-frequency front-end, to output a two-dimensional delay-Doppler accumulated power pattern comprising a plurality of accumulated powers corresponding to frequency and time; and

a processor coupled to the digital signal processing circuitry to determine, for a predetermined frequency, an average value of accumulated powers of the two-dimensional delay-Doppler accumulated power pattern over a plurality of time points by excluding accumulated power values at a maximum time point and two time points adjacent to the maximum;

wherein the processor generates a delay-Doppler accumulated power pattern with suppressed interference effect by subtracting the average value from the accumulated powers.

7. The receiver of claim 6 , wherein the processor is further programmed to repeat determining and subtracting for a plurality of frequencies thereby generating a two-dimensional delay-Doppler accumulated power pattern with suppressed interference effect.

8. The receiver of claim 6 , wherein the average value is an arithmetic mean, a median, or a mode.

9. The receiver of claim 6 , wherein the average value is obtained by referencing a lookup table.

10. The receiver of claim 6 , wherein a frequency is a Doppler bin of the two-dimensional delay-Doppler accumulated power pattern and a time point is a code bin of the two-dimensional delay-Doppler accumulated power pattern.

11. The receiver of claim 6 , wherein the processor is a 32 bit processor.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2021
From: MEDIATEK INC.
To: XUESHAN TECHNOLOGIES INC.
Reel/Frame 055443/0818 →
MERGER Recorded Apr 13, 2020
From: MSTAR SEMICONDUCTOR, INC.
To: MEDIATEK INC.
Reel/Frame 052381/0368 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2007
From: AQTRACK TECHNOLOGIES, INC.
To: MSTAR SEMICONDUCTOR, INC.
Reel/Frame 019471/0049 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2006
From: BOCHKOVSKIY, ANDREY; GOLOUBEV, MIKHAIL; POSPELOV, SERGEY; VASILYEV, MIKHAIL; TCHISTIAKOV, VALERI; KHOLOSTOV, MIKHAIL; NOZDRACHEV, SERGEY; MIKHAYLOV, NIKOLAY; JALALI, BIJAN
To: AQTRACK TECHNOLOGIES, INC.
Reel/Frame 017377/0618 →