Apparatus and method for detecting and recovering errors caused by electrostatic discharge
View Patent ↗A method and apparatus for detecting an error compares a hardwired reference value to a corresponding predetermined value and generates an error indication in response to a change in the predetermined value. In one embodiment, the predetermined value is set to be the same as the hardwired reference value and in response to an electrostatic discharge event or any other suitable cause of error, the predetermined value changes so that a comparison indicates that an error has occurred. An error indication is then generated which may be, for example, an interrupt to recovery logic that generates recovery control information to reset a functional block that was corrupted or to perform in an entire chip reset if desired.
1. A method for detecting an error comprising:
comparing, in an integrated circuit, a hardwired reference value to a corresponding predetermined value provided by a corresponding predetermined value circuit of the integrated circuit;
generating, in the integrated circuit, an error indication based on the comparison that detects a difference between the hardwired reference value and the predetermined value; and
performing, in the integrated circuit, a recovery process to recover a functional block in response to the generated error indication.
2. The method of claim 1 comprising; resetting the predetermined value to detect a subsequent error.
3. The method of claim 1 wherein the predetermined value is the same value as the hardwired reference value during normal operation and wherein generating the error indication based on the comparison comprises generating the error indication when the predetermined value and the hardwired reference value do not match.
4. The method of claim 1 wherein the hardwired reference value and the predetermined value are associated with one of a plurality of functional blocks in the integrated circuit and where the method further comprises performing the recovery process to recover the functional block in response to the generated error indication associated with the functional block.
5. The method of claim 4 wherein the error indication comprises an interrupt and wherein performing recovery of the functional block comprises generating recovery control information to reset the functional block.
6. A method for detecting an error comprising:
comparing, for each of at least a plurality of functional blocks in an integrated circuit, a hardwired reference value to a corresponding predetermined value, wherein a predetermined value circuit provides the corresponding predetermined value;
generating an error indication, on a per functional block basis, based on the comparison that results in a difference between the hardwired reference value and the corresponding predetermined value for a given functional block; and
for at least one of the functional blocks that caused the error indication, resetting the corresponding predetermined value to a value that matches the hardwired reference value in response to performing a recovery process to recover the at least one of the functional blocks that caused the error indication.
7. The method of claim 6
wherein each predetermined value is the same value as a corresponding hardwired reference value during normal operation and
wherein generating the error indication based on the comparison comprises generating the error indication when a predetermined value and corresponding hardwired reference value do not match.
8. The method of claim 6 wherein the method further comprises performing the recovery process to recover the at least one of the functional blocks in response to the generated error indication associated with the at least one of the functional blocks.
9. The method of claim 8 wherein the error indication comprises an interrupt and wherein performing the recovery process to recover a functional block comprises generating recovery control information to reset the functional block.
10. An integrated circuit comprising:
a circuit for detecting an error comprising:
a hardwired reference value circuit that provides a hardwired value;
a corresponding predetermined med value circuit that provides a predetermined value;
comparator logic, operatively coupled to the hardwired reference value circuit and the corresponding predetermined value circuit, and operative to compare a hardwired reference value to a corresponding predetermined value; and
error indication logic operative to generate an error indication based on the comparison that detects a difference between the hardwired reference value and the predetermined value.
11. The integrated circuit of claim 10 wherein the predetermined value is the same value as the hardwired reference value during normal operation and wherein the error generation logic generates the error indication when the predetermined value and the hardwired reference value do not match.
12. The integrated circuit of claim 10 comprising reset logic operatively responsive to recovery control information and operative to reset the predetermined value to a value that matches the corresponding hardwired reference value in response to recovery control information.
13. The integrated circuit of claim 10 comprising a plurality of functional blocks wherein each of the plurality of functional blocks comprises a respective circuit for detecting and comprising multi-functional block error detection status logic containing data representing which of the plurality of functional blocks detected an event based on respective circuits for detecting the error event.
14. A portable device comprising:
a first processor comprising a circuit for detecting an error comprising:
a hardwired reference value circuit that provides a hardwired value;
a corresponding predetermined value circuit that provides a predetermined value circuit;
comparator logic, operatively coupled to the hardwired reference value circuit and the corresponding predetermined value circuit, and operative to compare a hardwired reference value to a corresponding predetermined value; and
error indication logic operative to generate an error indication in response to a detected change in the predetermined, value;
a second processor, operatively coupled to the first processor, comprising:
error recovery logic operatively responsive to the error indication and operative to perform a recovery process to recover at least one of the entire first processor or at least one functional block in the first processor in response to the generated error indication.
15. The device of claim 14 wherein the error indication comprises an interrupt and wherein performing the recovery process to recover a functional block comprises generating recovery control information to reset the functional block.
16. The device of claim 14 wherein the predetermined value is the same value as the hardwired reference value during normal operation and wherein the error generation logic generates the error indication when the predetermined value and the hardwired reference value do not match.
17. The device of claim 14 comprising reset logic operatively responsive to recovery control information and operative to reset the predetermined value to a value that matches the corresponding hardwired reference value in response to recovery control information.
18. The device of claim 14 wherein the first processor comprises a plurality of functional blocks wherein each of the plurality of functional blocks comprises a respective circuit for detecting an error and wherein the first processor comprises multifunctional block error detection status logic containing data representing which of the plurality of functional blocks detected an error based on respective circuits for detecting the error.