Technique for expanding an input signal
View Patent ↗A technique for expanding an input signal includes receiving the input signal at a first node of a voltage expander and generating a plurality of expanded signals on different outputs of the voltage expander responsive to the input signal. In certain embodiments, each of the expanded signals has a different magnitude at a respective fixed offset from the input signal.
1. A circuit comprising:
a first node responsive to an input signal; and
a plurality of circuit branches, each comprising a respective resistor element coupled to the first node and arranged to develop a respective signal having a respective fixed offset relative to the first node, which fixed offset is determined by a respective controlled magnitude current flowing through the respective resistor element;
wherein each respective signal is conveyed to a respective one of a plurality of outputs,
wherein certain ones of said plurality of circuit branches cause a current to flow into the first node, and remaining ones of said plurality of circuit branches cause a current to flow from the first node.
2. The circuit of claim 1 wherein an aggregate current flowing into the first node through said certain ones of the circuit branches is substantially identical to an aggregate current flowing from the first node through said remaining ones of the circuit branches.
3. The circuit of claim 1 wherein said certain ones of the circuit branches and said remaining ones of the circuit branches are equal in number.
4. The circuit of claim 1 wherein the output signals are voltages nominally centered about the input signal voltage.
5. The circuit of claim 1 wherein a signal on the first node is conveyed to another one of the plurality of outputs.
6. The circuit of claim 5 wherein the output signals are substantially evenly-spaced voltages.
7. The circuit of claim 1 wherein each of the plurality of circuit branches further comprises a respective current mirror circuit coupled to a source of voltage and further coupled to the respective resistor element.
8. The circuit of claim 7 further comprising:
an input node for receiving the input signal; and
a buffer circuit having an input coupled to the input node and having an output coupled to the first node.
9. A circuit comprising:
a first node responsive to an input signal; and
means for generating a plurality of expanded signals on a corresponding plurality of outputs, each of the expanded signals having a respective magnitude at a respective fixed offset from that of the first node, wherein the magnitude of each of the expanded signals is related to the input signal when such expanded signal is within a certain range.
10. The circuit of claim 9 wherein each respective fixed offset is determined by a respective controlled magnitude current flowing through a respective resistor element.
11. The circuit of claim 9 wherein the expanded signals are output voltages and the input signal is an input voltage, and wherein the output voltages are nominally centered about the input voltage.
12. The circuit of claim 9 wherein the expanded signals are substantially evenly-spaced output voltages.
13. The circuit of claim 9 wherein a signal on the first node is conveyed as another output signal.
14. The circuit of claim 13 wherein the output signals are substantially evenly-spaced output voltages.
15. The circuit of claim 9 wherein the circuit is encoded on one or more computer readable medium.
16. The circuit of claim 9 further comprising:
a tunable LC tank circuit including a variable capacitance circuit having a plurality of inputs, wherein a different one of the expanded signals is provided to each of the respective inputs of the variable capacitance circuit.
17. A method for expanding an input signal, said method comprising:
providing a first node responsive to an input signal; and
developing a plurality of signals, each respective signal having a respective fixed offset relative to the first node, which fixed offset is determined by flowing a respective controlled magnitude current through a respective resistor element;
conveying each respective signal to a respective one of a plurality of outputs,
wherein the output signals are output voltages and the input signal is an input voltage, and wherein the output voltages are nominally centered about the input voltage.
18. The method of claim 17 wherein the output signals are substantially evenly-spaced voltages.
19. The method of claim 17 further comprising:
conveying a signal on the first node to another one of the plurality of outputs; and
developing output signals having a magnitude both greater than and less than the magnitude of the first node.