IP Library Granted Patent US 7,644,343
Granted Patent B2
US 7,644,343 · App. 11/279,683 · Granted Jan 5, 2010

Error resilience methods for multi-protocol encapsulation forward error correction implementations

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Quick Facts
Patent No.
US 7,644,343
App. No.
11/279,683
Granted
Jan 5, 2010
Kind
B2
Abstract

Transport stream (TS) packets containing sections of IP datagrams for an application level process are received and correct ones of said sections are stored into an MPE-FEC frame buffer of a receiver. Stored ones of said sections are reorganized within the frame buffer so as to leave appropriate positions, marked for erasure, within the frame buffer available for corrected data. Data bytes stored at the appropriate positions may be corrected using Reed-Solomon parity data stored in the frame buffer and then subsequently written back thereto.

Claims (7)

1. A method, comprising receiving TS packets containing sections of IP datagrams for an application level process, storing correct ones of said sections into an MPE-FEC frame buffer of a receiver; reorganizing stored ones of said sections within the MPE-FEC frame buffer so as to leave appropriate positions within the MPE-FEC frame buffer available for corrected data; and marking for erasure the appropriate positions.

2. The method of claim 1 , further comprising correcting data bytes stored at the appropriate positions marked for erasure in the MPE-FEC frame buffer using Reed-Solomon parity data stored in the MPE-FEC frame buffer.

3. The method of claim 2 , further comprising writing back to the MPE-FEC frame buffer, at the appropriate locations marked for erasure, the data bytes corrected using the Reed-Solomon parity data.

4. The method of claim 1 , wherein the sections of IP datagrams are stored into the MPE-FEC frame buffer according to locations indicated by an MPE-FEC frame buffer write pointer, said write pointer being adjusted for TS packet errors and new MPE section starts observed at the receiver, and the appropriate locations within the MPE-FEC frame buffer are marked for erasure on a byte-by-byte basis according to stored information concerning locations of said write pointer when said TS packet errors and new MPE section starts were observed.

5. The method of claim 1 , wherein the appropriate locations within the MPE-FEC frame buffer are marked for erasure according to reliability information regarding said sections of IP datagrams stored separately therefrom.

6. The method of claim 5 , wherein the reliability information comprises entries for only erasure blocks in the MPE-FEC frame buffer.

7. The method of claim 5 , wherein the reliability information comprises entries for only non-erasure blocks in the MPE-FEC frame buffer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 14, 2024
From: CSR TECHNOLOGY INC.
To: QUALCOMM INCORPORATED
Reel/Frame 069221/0001 →
CHANGE OF NAME Recorded Dec 22, 2011
From: SIRF TECHNOLOGY, INC.
To: CSR TECHNOLOGY INC.
Reel/Frame 027437/0324 →