Thin film transistor and method of fabricating the same
View Patent ↗A thin film transistor and method of fabricating the same are provided. In the thin film transistor, a seed or a grain boundary exists in a semiconductor layer pattern but not in a junction region. The method includes forming a semiconductor layer pattern. Forming the semiconductor layer pattern includes: forming and patterning a first capping layer on an amorphous silicon layer; forming a second capping layer on the first capping layer pattern; forming a metal catalyst layer on the second capping layer; diffusing the metal catalyst; and crystallizing the amorphous silicon layer to form a polysilicon layer. Therefore, it is possible to prevent that a trap is generated in the junction region, thereby obtaining improved and uniform characteristics of the device.
1. A method of fabricating a thin film transistor, comprising:
forming an amorphous silicon layer on a substrate;
crystallizing and patterning the amorphous silicon layer to form a semiconductor layer pattern, the semiconductor layer pattern comprising a source region, a drain region, and a channel;
forming a gate insulating layer on the semiconductor layer pattern; and
forming a gate electrode on the gate insulating layer,
wherein a seed or a grain boundary exists in the semiconductor layer pattern but a junction region in the semiconductor layer pattern wherein the source region and the channel meet and the drain region and the channel meet does not have a grain boundary.
2. The method according to claim 1 , wherein the seed or the grain boundary in the semiconductor layer pattern exists in an active region of the semiconductor layer pattern.
3. The method according to claim 1 , wherein forming the semiconductor layer pattern comprises:
forming and patterning a first capping layer on the amorphous silicon layer;
forming a second capping layer on the first capping layer pattern;
forming a metal catalyst layer on the second capping layer;
diffusing the metal catalyst; and
crystallizing the amorphous silicon layer to form a polysilicon layer.
4. The method according to claim 3 , wherein the first capping layer is patterned such that the seed is formed within 1 to 3 μm from the junction region in a direction of a contact hole.
5. The method according to claim 3 , wherein the first capping layer pattern is formed of any one of a silicon nitride layer and a silicon oxide layer.
6. The method according to claim 3 , wherein the second capping layer is formed of any one of a silicon nitride layer and a silicon oxide layer.
7. The method according to claim 3 , wherein the first capping layer pattern is thicker than the second capping layer.
8. The method according to claim 3 , wherein the first capping layer pattern has a higher density than the second capping layer.
9. The method according to claim 3 , wherein the first capping layer and the second capping layer are formed by a plasma enhanced chemical vapor deposition (PECVD) method.
10. The method according to claim 3 , wherein the metal catalyst is formed of nickel (Ni).
11. The method according to claim 3 , wherein the metal catalyst layer is formed by any one of a chemical vapor deposition (CVD) method and a sputtering method.
12. The method according to claim 3 , wherein the diffusion of the metal catalyst is performed by an annealing process.
13. The method according to claim 12 , wherein the annealing process is performed at a temperature of 200 to 700° C.
14. The method according to claim 3 , wherein the amorphous silicon layer is crystallized by an annealing process.
15. The method according to claim 14 , wherein the annealing process is performed at a temperature of 400 to 1000° C.
16. The method according to claim 1 , further comprising forming a buffer layer between the substrate and the amorphous silicon layer.