Technique to increase the speed of a peak detector

1. A peak detector comprising:

a differential signal input circuit;

a storage device connected to the differential signal input circuit, the storage device charging/discharging based on a charging current provided by the differential signal input circuit;

a sensing device for sensing the charging current;

an active discharge device connected to the storage device; and

a control circuit, responsive to the sensing device, for controlling the active discharge device, the control circuit including a plurality of current mirrors,

wherein the active discharge device reduces a discharge current in response to an increased charging current, and wherein the active discharge device increases a discharge current in response to a decreased charging current.

2. The peak detector of claim 1 , wherein the sensing device includes a p-type transistor.

3. The peak detector of claim 1 , wherein the active discharge device include an n-type transistor.

4. A peak detector comprising:

an RF differential signal input circuit;

a capacitor connected to the RF differential signal input circuit, the capacitor charging/discharging based on a charging current provided by the RF differential signal input circuit;

a sensing device for sensing the charging current;

an active discharge device connected to the capacitor; and

a control circuit, responsive to the sensing device, for controlling the active discharge device, the control circuit including a plurality of current mirrors,

wherein the active discharge device reduces a discharge current in response to an increased charging current, and wherein the active discharge device increases a discharge current in response to a decreased charging current.

5. The peak detector of claim 4 , wherein the sensing device includes a p-type transistor.

6. The peak detector of claim 4 , wherein the active discharge device include an n-type transistor.

7. A peak detector comprising:

a first n-type transistor having a source, a drain, and a gate, the gate for receiving a positive differential signal;

a second n-type transistor having a source, a drain, and a gate, the gate for receiving a negative differential signal;

a first p-type transistor having a source, a drain, and a gate, the source connected to a first voltage source, and the drain connected to the drains of the first and second n-type transistors;

a third n-type transistor having a source, a drain, and a gate, the source connected to a second voltage source, and the drain connected to the sources of the first and second n-type transistors and an output terminal;

a capacitor connected between the output terminal and the second voltage source;

a current source connected between the first voltage source and a first node;

a fourth n-type transistor having a source, a drain, and a gate, the source connected to the second voltage source, and the drain and gate connected to the first node and the gate of the third n-type transistor;

a second p-type transistor having a source, a drain, and a gate, the source connected to the first voltage source, and the gate connected to the gate of the first p-type transistor;

a fifth n-type transistor having a source, a drain, and a gate, the source connected to the second voltage source, and the drain and gate connected to the drain of the second p-type transistor; and

a sixth n-type transistor having a source, a drain, and a gate, the source connected to the second voltage source, the drain connected to the first node, and the gate connected to the gate of the fifth n-type transistor.

8. A peak detector comprising:

a first n-type transistor having a source, a drain, and a gate, the gate for receiving a positive differential signal;

a second n-type transistor having a source, a drain, and a gate, the gate for receiving a negative differential signal;

a first p-type transistor having a source, a drain, and a gate, the source connected to a first voltage source, and the drain and the gate connected to the drains of the first and second n-type transistors;

a third n-type transistor having a source, a drain, and a gate, the source connected to a second voltage source, and the drain connected to the source of the first n-type transistor;

a fourth n-type transistor having a source, a drain, and a gate, the source connected to the second voltage source, and the drain connected to the source of the second n-type transistor;

a first capacitor having a first terminal for receiving the negative differential signal and a second terminal connected to the source of the first n-type transistor as well as the drain of the third n-type transistor;

a second capacitor having a first terminal for receiving the positive differential signal and a second terminal connected to the source of the second n-type transistor as well as the drain of the fourth n-type transistor;

a first resistor and a second resistor connected in series between the second terminals of the first and second capacitors;

a first node connected to an output terminal;

a third capacitor connected between the first node and the second voltage source;

a current source connected between the first voltage source and a second node;

a fifth n-type transistor having a source, a drain, and a gate, the source connected to the second voltage source, and the drain and the gate connected to the gates of the third and fourth n-type transistors;

a second p-type transistor having a source, a drain, and a gate, the source connected to the first voltage source, and the gate connected to the gate of the first p-type transistor;

a sixth n-type transistor having a source, a drain, and a gate, the source connected to the second voltage source, and the drain and source connected to the drain of the second p-type transistor; and

a seventh n-type transistor having a source, a drain, and a gate, the source connected to the second voltage source, the drain connected to the second node, and the gate connected to the gate of the sixth n-type transistor.