Method and apparatus for providing efficient output buffering and bus speed matching

1. An interconnect apparatus comprising a transaction packet buffer and control logic operable sequentially to write transaction packets for transmission to the transaction packet buffer and operable to transmit the buffered transaction packets in sequence to a destination, the control logic farther being operable to:

on receipt of a control packet indicative of non-receipt by the destination of a transmitted transaction packet to retransmit the non-received transaction packet and transaction packets transmitted from the transaction packet buffer subsequent to the non-received transaction packet;

in response to the absence of a control packet indicative of non-receipt by the destination of a transmitted transaction packet within a predetermined period to retransmit the transaction packets transmitted from the transaction packet buffer subsequent to a transaction packet for which an acknowledgment of receipt from the packet destination was last received;

wherein the control logic comprises an address buffer, each entry in the address buffer identifying a location in the transaction packet buffer at which a corresponding transaction packet is stored; and

wherein the control logic comprises a read pointer indicating an address buffer entry for a next transaction packet to be transmitted, a write pointer indicating an address buffer entry for a next transaction packet to be added to the buffer, and a last acknowledged sequence number pointer indicating an address buffer entry for the transaction packet having a sequence number for which an acknowledgment of receipt from the packet destination was last received.

2. The interconnect apparatus of claim 1 , wherein the control logic identifies transaction packets in the transaction packet buffer that have been transmitted and transaction packets yet to be transmitted.

3. The interconnection apparatus of claim 1 , wherein each transaction packet is allocated a sequence number from a range of N sequence numbers.

4. The interconnect apparatus of claim 1 , wherein the control logic is operable to update the last acknowledged sequence number pointer in response to receipt of an acknowledgement indicative of a transmitted transaction packet having been received at the destination.

5. The interconnect apparatus of claim 1 , operable under a PCI Express protocol.

6. The interconnect apparatus of claim 1 , wherein the transaction packet is a transaction layer packet and the control packet is a data layer packet.

7. The interconnect apparatus of claim 2 , wherein the control logic is operable to identify a transaction packet buffer location to which a next transaction packet is to be stored in the buffer and is operable to identify a transaction packet buffer location from which a next transaction packet is to be transmitted.

8. The interconnection apparatus of claim 3 , wherein the address buffer comprises M×N entries.

9. The interconnect apparatus of claim 7 , wherein the control logic is operable to identify a transaction packet buffer location in which the transaction packets most recently transmitted for which an acknowledgment of receipt from the packet destination was received.

10. The interconnection apparatus of claim 8 , wherein the sequence numbers correspond to lower order address bits of addresses of the address buffer entries.

11. A computer system including an interconnect apparatus comprising a transaction packet buffer and control logic operable to write sequentially transaction packets for transmission to the transaction packet buffer and operable to transmit the buffered transaction packets in sequence to a destination, the control logic further being operable to:

on receipt of a control packet indicative of non-receipt by the destination of a transmitted transaction packet to retransmit the non-received transaction packet and transaction packets transmitted from the transaction packet buffer subsequent to the non-received transaction packet;

in response to the absence of a control packet indicative of non-receipt by the destination of a transmitted transaction packet within a predetermined period to retransmit the transaction packets transmitted from the transaction packet buffer subsequent to a transaction packet for which an acknowledgment of receipt from the packet destination was last received;

wherein the control logic comprises an address buffer, each entry in the address buffer identifying a location in the transaction packet buffer at which a corresponding transaction packet is stored; and

wherein the control logic comprises a read pointer indicating an address buffer entry for a next transaction packet to be transmitted, a write pointer indicating an address buffer entry for a next transaction packet to be added to the buffer, and a last acknowledged sequence number pointer indicating an address buffer entry for the transaction packet having a sequence number for which an acknowledgment of receipt from the packet destination was last received.

12. A method of providing output buffering and speed matching for an interconnect apparatus, the method comprising:

writing sequentially transaction layer packets for transmission to a transaction layer packet buffer and transmitting the buffered transaction packets in sequence to a destination;

on receipt of a control packet indicative of non-receipt by the destination of a transmitted transaction layer packet, retransmitting the non-received transaction packet and transaction layer packets transmitted from the transaction layer packet buffer subsequent to the non-received transaction packet;

in response to the absence of a control packet indicative of non-receipt by the destination of a transmitted transaction packet within a predetermined period, retransmitting the transaction packets transmitted from the transaction packet buffer subsequent to a transaction packet for which an acknowledgment of receipt from the packet destination was last received;

wherein the interconnect apparatus comprises an address buffer, each entry in the address buffer identifying a location in the transaction packet buffer at which a corresponding transaction packet is stored; and

wherein the interconnect apparatus comprises a read pointer indicating an address buffer entry for a next transaction packet to be transmitted, a write pointer indicating an address buffer entry for a next transaction packet to be added to the buffer, and a last acknowledged sequence number pointer indicating an address buffer entry for the transaction packet having a sequence number for which an acknowledgment of receipt from the packet destination was last received.